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Design Languages >> Verilog-AMS >> Osc v-ams code
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Message started by jugemu1234 on Mar 9^th, 2010, 6:43pm

Title: Osc v-ams code
Post by jugemu1234 on Mar 9^th, 2010, 6:43pm

Hi,

Can anybody help me debugging following code? When I run this, it ends up DC convergence error around pll_rstb node.
These code might look mess. if there is anyway to make this simpler/better, it would be appreciated.

---------------------------------------------
`include "constants.vams"
`include "disciplines.vams"

`timescale 1ps/1ps

module rosc ( clk, pll_rstb, test_out, dvdd, dvss, en, enExt, extClk, ib_1u, testEn, trim, turbo, turbo_div8, f160M );

input [7:0] trim;
input testEn, enExt, ib_1u, dvdd, dvss, extClk, en, turbo, turbo_div8;
output clk, pll_rstb, test_out, f160M;

logic [7:0] trim;
logic testEn, enExt, en, turbo, turbo_div8;
electrical ib_1u, dvdd, dvss, clk, f160M, test_out, extClk, pll_rstb;

real rin, half_period, freq, adj, jitter, ibias, period, int_clk, int_clk_div8, int_clk_div16, int_clk_div64, int_clk_div512;
integer seed, tgl0, tgl1, tgl2, tgl3, tgl4, tgl5;

analog begin

ibias=9*I(dvdd,ib_1u);
adj=ibias*4;

if(trim[7]) adj = adj-ibias*2.56;
if(trim[6]) adj = adj+ibias*1.28;
if(trim[5]) adj = adj+ibias*0.64;
if(trim[4]) adj = adj+ibias*0.32;
if(trim[3]) adj = adj+ibias*0.16;
if(trim[2]) adj = adj+ibias*0.08;
if(trim[1]) adj = adj+ibias*0.04;
if(trim[0]) adj = adj+ibias*0.02;

//frequency
freq = 3.5E12*adj+3.4E7;
half_period= 0.5/freq;

@(timer(half_period, half_period))
tgl0=!tgl0;
int_clk = V(dvdd,dvss) * transition(tgl0, 0.0, 100p, 100p);

@(timer(half_period*8, half_period*8))
tgl1=!tgl1;
int_clk_div8 = V(dvdd,dvss) * transition(tgl1, 0.0, 100p, 100p);

@(timer(half_period*16, half_period*16))
tgl2=!tgl2;
int_clk_div16 = V(dvdd,dvss) * transition(tgl2, 0.0, 100p, 100p);

@(timer(half_period*64, half_period*64))
tgl3=!tgl3;
int_clk_div64 = V(dvdd,dvss) * transition(tgl3, 0.0, 100p, 100p);

@(timer(half_period*512, half_period*512))
tgl4=!tgl4;
int_clk_div512 = V(dvdd,dvss) * transition(tgl4, 0.0, 100p, 100p);

//$display ("freq is %g", freq ) ;
//$display ("int_clk is %g", int_clk);
//$display ("adj is %g", adj);

if(enExt) begin
V(clk)<+ V(extClk);
end else begin
if(!en) begin
V(f160M)<+0;
V(clk)<+0;
V(test_out)<+0;
V(pll_rstb)<+0;
end else begin
if(turbo) begin
V(f160M)<+int_clk;
if (turbo_div8) V(clk)<+int_clk_div8;
else V(clk)<+int_clk_div16;
V(test_out)<+int_clk_div64;
V(pll_rstb)<+0;
end else begin
V(f160M)<+0;
V(clk)<+int_clk_div8;
V(test_out)<+int_clk_div512;
if(int_clk_div512 > 0.75)) begin
V(pll_rstb)<+V(dvdd,dvss);
end

end
end
end

end

endmodule

Title: Re: Osc v-ams code
Post by boe on Mar 10^th, 2010, 6:39am

jugemu1234,
I noticed the following issues (without trying to run it):

Code:

//frequency
freq = 3.5E12*adj+3.4E7;
half_period= 0.5/freq;

Do you really mean 3.5e12 !???

Code:

if(enExt) begin
V(clk)<+ V(extClk);
end ...

In this case V(f160M), V(test_out) and V(pll_rstb) are unassigned...

BOE

Title: Re: Osc v-ams code
Post by Geoffrey_Coram on Mar 10^th, 2010, 7:13am

... and since they're unassigned, they default to open-circuits -- that is, pll_rstb is effectively floating (has no connection to ground through the module).

Title: Re: Osc v-ams code
Post by jugemu1234 on Mar 10^th, 2010, 10:48pm

Thanks guys. Simulation runs now.

Btw, New issue came up. I added jitter statement as in following code, but all outputs look not toggling. Displaying intermediate variable "half_period", it seems fine because I can see that randomness was added centered around wanted period. What is the problem with this?

Code:

//frequency
freq = 3.5E12*adj+3.4E7;
//jitter
jt = 1p*$rdist_normal(seed, jt_mean, jt_stdev);
//Half period
//half_period=(0.5/freq); //without random jitter
half_period=(0.5/freq+jt); //with random jitter
//time offset
toffset= 1.5E-6;

@(timer(half_period+toffset, half_period))
tgl0=!tgl0;
int_clk = V(dvdd,dvss) * transition(tgl0, 0.0, 100p, 100p);

Title: Re: Osc v-ams code
Post by Marq Kole on Mar 22^nd, 2010, 1:35am

My guess for the output not toggling is that the start time of the timer is dynamic - after the timer has become active the time expression is updated to a value in the past which essentially switches off the timer, even though the period argument would suggest to repeat with given (updated) period. The way around this is to make sure the time expression stays ahead of the current simulation time:

Code:

...

@(initial_step) last_cross = toffset;

@(timer(last_cross + half_period)) begin
last_cross = $abstime;
tgl0=!tgl0;
end

Now the time expression is always into the future.

You can improve accuracy by using the last_crossing operator.

Cheers,
Marq