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Design >> Analog Design >> CML/SCL layout
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Message started by oermens on Mar 11th, 2010, 12:33pm

Title: CML/SCL layout
Post by oermens on Mar 11th, 2010, 12:33pm

Hi, I want to do layout of some CML gates. Since there are no standard cells for this logic family (or are there?), what is the best way to do the layout? I figure symmetry is important, what else? Should transistors be drawn on a single active, or as they are arranged in schematic (stacked diff pairs)? Would each diff pair need its own guard ring?

My design works in UHF range.

Thanks.

Title: Re: CML/SCL layout
Post by love_analog on Apr 7th, 2010, 9:45pm

typically you do common-centriod on the transistors for matching.

I haven't heard of anyone having a "CML" library from a fab.

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