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Design >> Analog Design >> MosCap
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Message started by siddhartha .k on Mar 22^nd, 2010, 8:26am

Title: MosCap
Post by siddhartha .k on Mar 22^nd, 2010, 8:26am

HI what is advantages using nmoscap insted of MOSFET

Title: Re: MosCap
Post by pancho_hideboo on Mar 22^nd, 2010, 8:30am

GaAs_si wrote on Mar 22^nd, 2010, 8:26am:

HI what is advantages using nmoscap insted of MOSFET

I can't understand meaning of your question.

If your design kit have nmoscap for MOS Capacitor, accuracy of modeling as capactor is far good compared to MOSFET.

Title: Re: MosCap
Post by panditabupesh on Mar 26^th, 2010, 1:37pm

Look at the capacitance versus gate voltage plot. For nmoscap the gate voltage is closer to zero and that means your C versus V trough is pushed to lower gate voltage.

Bupesh

Title: Re: MosCap
Post by pancho_hideboo on Mar 26^th, 2010, 2:04pm

panditabupesh wrote on Mar 26^th, 2010, 1:37pm:

For nmoscap the gate voltage is closer to zero
and that means your C versus V trough is pushed to lower gate voltage.

It depends on Vt of MOSFET.

So I don't think CV characteristics of "nmoscap" always shows low Vt MOSCap.

Title: Re: MosCap
Post by panditabupesh on Mar 26^th, 2010, 5:52pm

"nmoscap" is a term used by most of the foundries for capacitor formed by a NMOS in NWELL. And my reply about the CV characteristics was based on this assumption.

Bupesh

Title: Re: MosCap
Post by pancho_hideboo on Mar 27^th, 2010, 12:14am

panditabupesh wrote on Mar 26^th, 2010, 5:52pm:

"nmoscap" is a term used by most of the foundries for capacitor formed by a NMOS in NWELL.

I don't think so.

Attached is a device structure from "gpdk180_DRM.pdf" of Cadence GPDK180.
Here a term of "nmoscap" is used for "NMOS transistor configured as a capacitor".

Release Date: 2008/09/24
Revision: 3.3
PDK: gpdk180_v3.3.tar.gz

Title: Re: MosCap
Post by pancho_hideboo on Mar 27^th, 2010, 12:15am

panditabupesh, maybe you mean structure like attached figure.

But this capacitor is called as "pcdcap" in major foundry.
Sometimes this is also called as nMOS varactor (ncap) and thick oxide nMOS varactor (dgncap).

We can't judge structure from "name".

Title: Re: MosCap
Post by oermens on Mar 27^th, 2010, 9:46pm

the "major foundry" which uses the name "ncap/dgncap" is for nfet in nwell. i just installed 65nm and 90nm pdks from a different major foundry, they provide nmoscap (nfet in nwell) and moscap_rf. i haven't used the new pdks yet, not sure what the moscap_rf structure is. as far as i've read (in pdk documentation, not generally), they are all standard-vt devices.

Title: Re: MosCap
Post by Nimrod Ben-Ari on Apr 21^st, 2010, 2:25am

Hi,
in TSMC and Tower process NMOSCAP refers to Gate oxide over Nwell capacitor, the advantage over PMOS capacitor is that instead of having P+ implants for the Drain/Source and N+ for the bulk you only have N+ implants - thus you reduce the required area, also we saw that the capacitor have slightly better C/Area ratio compared to PMOS with the same gate area, but I never looked for the reason.

Nimrod

Title: Re: MosCap
Post by Mayank on Apr 21^st, 2010, 7:33am

Hi NimRod,

Quote:

we saw that the capacitor have slightly better C/Area ratio compared to PMOS with the same gate area, but I never looked for the reason.

Most Probable reason for this is that NMOSCAP has a thicker gate oxide as compared to NMOS so as to boost its Cap / Area ratio. Just Check.

Quote:

the advantage over PMOS capacitor

Both nmosCAP & pmosCAP are non-linear caps whose Impedance varies with the DC voltage on the Gate of the device.
PMOSCAP gives max capacitance near low Voltages & vice versa for NMOSCAP.
on the DC Voltage at the node on which u wanna plug a cap, Use NMOSCAP / PMOSCAP / A combo of both.

--
Mayank.

Title: Re: MosCap
Post by Geoffrey_Coram on May 7^th, 2010, 5:11am

Mayank wrote on Apr 21^st, 2010, 7:33am:

Hi NimRod,

Quote:

we saw that the capacitor have slightly better C/Area ratio compared to PMOS with the same gate area, but I never looked for the reason.

Most Probable reason for this is that NMOSCAP has a thicker gate oxide as compared to NMOS so as to boost its Cap / Area ratio. Just Check.

That doesn't make sense to me. Thicker oxide would mean lower capacitance (C = εA/d, where d is the distance between the plates).