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Design Languages >> Verilog-AMS >> Compatibility with Hspice
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Message started by mohammadfawaz on Mar 22^nd, 2010, 2:07pm

Title: Compatibility with Hspice
Post by mohammadfawaz on Mar 22^nd, 2010, 2:07pm

Hello all,

I'm new to Verlilog A, and I'm having a problem when trying to compile models that are clock depending such as a counter. How can I use a clock in a model and still be able to use the model in HSPICE?

Thank you

Title: Re: Compatibility with Hspice
Post by Marq Kole on Mar 23^rd, 2010, 2:29am

1. Define an input for the clock signal

Code:

inout clk;
electrical clk;

2. Create an event that checks for the clock's edges:

Code:

@(cross(V(clk) - thresh, +1)) begin
count = (count > max_count) ? 0 : count + 1;
outval = (count == 0);
end

3. Contribute a value calculated in the event statement to the output

Code:

V(out) <+ outval;

Hope this helps,
Marq

Title: Re: Compatibility with Hspice
Post by mohammadfawaz on Mar 23^rd, 2010, 2:56pm

Hello,

When I try to compile this using HSPICE, I'm getting an error at "@".
I have HSPICE A-2008.03. Should I have a new version?

Thank you

Title: Re: Compatibility with Hspice
Post by mohammadfawaz on Mar 23^rd, 2010, 3:09pm

Problem solved. I have a problem with includes..
thanx