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Design >> Analog Design >> dummypoly on 65nm
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Message started by siddhartha .k on Mar 24^th, 2010, 11:11am

Title: dummypoly on 65nm
Post by siddhartha .k on Mar 24^th, 2010, 11:11am

Hi Why a dummy poly is necessary on each side of 65nm transistors
Even matching is not requited ?

Title: Re: dummypoly on 65nm
Post by sv on Mar 26^th, 2010, 2:43pm

I think you are talking about dummy fingers that you see on the ends of the pcell of 65nm and not about dummy devices that you see recommended in any analog design textbook. If so, read on

Deep submicron CMOS transistors (typically 0.130um and bellow) exhibit stress effects, called as LOD effect and such. Stress effects result from shallow trench isolation (STI) and other processing steps employed to create these transistors. I would highly recommend reading up some papers to get familiar with those.

As a result, threshold voltage (VT) of a finger is dependent on the distance of that finger from the edge of the transistor (the "OD" layer). Thus if you create a 10-finger transistor each of those 10 fingers would have different threshold voltages depending on how far they are from the edge of OD. A well designed PDK with BSIM4 model will compute this for you based of geometry parameter information passed by the netlister.

People employ several strategies to deal with it for matching transistors. One way is construct the layout pcell such that it has 1,2 or 3 dummy fingers on the each end of the transistor. It can work because those dummy fingers on the end are the ones seeing maximum stress and once you leave the 1,2 or 3 dummy fingers on the end, the rest of the fingers in the middle of the pcell see approximately the same stress.

Obviously this results into some wastage of area because every pcell is carrying these dummy fingers. In my opinion this is not the only way to deal with it. If you want you can construct you matched pairs with unit sized transistors without any dummy fingers. Because every unit transistor has the same layout, they will see the same stress and therefore match.

As an example let us say that you are creating a 10:1 currrent mirror. In the first way you will create 2 transistors, one with 1 finger + 4 dummies and second with 10 fingers + 4 dummies. Using the second way, you will construct it by using 11 single fingered transistors and no dummies (but the OD layers of these 11 transistors can not be shared.)

Any additions/corrections welcome.

Title: Re: dummypoly on 65nm
Post by loose-electron on Mar 26^th, 2010, 3:51pm

matching data is going to be very unique to a particular foundry-process situation.

Very dangerous to generalize. The "bigger is better", generally still holds , but nothing quantitative. Also, beyond a certain size, doesn't mean that the matching keeps improving.

Bottom Line - Get the specific data for your foundry-process, get specifics on matching and the layout conditions for that matching data.

Title: Re: dummypoly on 65nm
Post by love_analog on Apr 7^th, 2010, 9:35pm

SV
I do not think you are entirely correct. I agree with loose_electron - go with what your foundry specifies as their matching guidelines

for istance, they may spec that you need 3 dummies on either side. This is the only transistor structure which they have characterized in their lab as having good matching.
If you try to fiddle by using, say common-centroid or some other method to save area, you may think you have a good structure but the foundry hasn't characterized it and perhaps in this fab, there are other effects.