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Design >> RF Design >> ADC sensitivity to duty cycle?
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Message started by Steve_S on Mar 26^th, 2010, 9:34pm

Title: ADC sensitivity to duty cycle?
Post by Steve_S on Mar 26^th, 2010, 9:34pm

Hi, I am presently characterizing a pipeline ADC.
It was designed to operate at 125 Mhz.
When I run at 62.5 Mhz, the converter meets all specifications.
When I run at 125 Mhz, the noise floor rises by about 6 db and I lose about 1 bit of ENOB.
The noise floor appears to have low level harmonics of the input frequency.
I suspect problems with the duty cycle of the clock input.
Does that make sense? If not, I'd appreciate suggestions.

Title: Re: ADC sensitivity to duty cycle?
Post by sheldon on Mar 26^th, 2010, 11:12pm

Steve,

First question, when you say that is was designed to operate at 125MHz, how did you verify
the SINAD at 125MHz?

Next suppose that the front-end, S/H, that the duty cycle is 40%/60% instead of 50%/50%,
then effectively it is operating at 156.25MHz instead of 125MHz. That is, instead of 4ns to acquire
and 4ns to settle [hold], there are now 3.2ns(4.8ns) to acquire and 4.8ns(3.2ns) to settle.
Reducing the amount of time to perform either operation will increase the distortion, due to
incomplete settling. When you designed the ADC did you allocate margin for duty cycle variation?

Best Regards,

Sheldon

Title: Re: ADC sensitivity to duty cycle?
Post by Steve_S on Mar 26^th, 2010, 11:34pm

We designed it to settle to 13 bits (1 additional bit). I guess my question has more to do with the manifestation of incomplete settling. For example, with a 125 Mhz Fs and a 1 Mhz Fin, would incomplete settling results in harmonics which appear throughout the 62.5 Mhz range of the Nyquist frequency. In my measurements, this harmonic distortion raises the noise floor by 6dB. If this is the case, and we know that the OTA were designed to settle with 13 bits of resolution (assuming a 50% duty cycle), can we predict the amount the duty cycle is distorted?

Title: Re: ADC sensitivity to duty cycle?
Post by sheldon on Mar 28^th, 2010, 7:22pm

Steve,

My expectation is that incomplete settling would cause odd harmonics.
The effect of incomplete settling is largest at zero-crossing points on
the sine wave, where the slew rate is highest. In addition, the harmonics
should increase as the input frequency increases since the slew rate
increases.

Best Regards,

Sheldon

Title: Re: ADC sensitivity to duty cycle?
Post by Steve_S on Mar 28^th, 2010, 10:49pm

Hi Sheldon,

I've been thinking about this since Friday and I have to agree.
The issue isn't duty cycle (necessarily) but rather incomplete settling.
I plan to do more measurements (this week) with higher input frequencies.

I'll also get a simulation running with even an even higher sampling rate to
look at the effects on the passband noise floor when the converter is being stressed.

Thanks for your comments.

Steve

Title: Re: ADC sensitivity to duty cycle?
Post by love_analog on Apr 22^nd, 2010, 4:40pm

Hi Steve
Can you please share your results. I would be curious to know what you found out. I don't think its duty cycle related ...