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Design >> Analog Design >> Self-biased current mirror question
https://designers-guide.org/forum/YaBB.pl?num=1269696843

Message started by Visjnoe on Mar 27^th, 2010, 6:34am

Title: Self-biased current mirror question
Post by Visjnoe on Mar 27^th, 2010, 6:34am

Dear all,

I have a question on a self-biased current mirror scheme which I often see in papers (see picture).

How is this structure intended to operate?

When you use devices with the same VT, you can easily see that the bottom transistor will always reside in the linear region.
OK, this is a form of 'degeneration', but linearity is usually
not so important when it comes to biasing current mirrors.
Also, when I perform handcalculations on the structure with
the bottom transistor in the linear region, I find you don't gain
much in terms of output impedance.

However, when you use a low-VT device in combination with a high-VT device, you can size this structure as a cascoded current mirror with the well-known 'gm*ro1*ro2' output impedance effect.

What is your opinion/experience on the intended operation of this structure?

Regards

Title: Re: Self-biased current mirror question
Post by loose-electron on Mar 28^th, 2010, 4:49pm

what you have drawn there is the electrical equivalent of a devive where the channel length (of the equivalent circuit) is essentially Lnew = Ltran X 2

Channel length got doubled in the bias configuration shown

Title: Re: Self-biased current mirror question
Post by Visjnoe on Mar 29^th, 2010, 7:11am

Thanks for this comment.

Do you have any literature reference where this configuration is discussed in more detail? I still wonder about the operating region of both transistors in this configuration.

Regards

Title: Re: Self-biased current mirror question
Post by aaron_do on Mar 29^th, 2010, 7:51am

I'm not sure there is any need for any literature. As mentioned you can simply treat the two devices as a single device with double the channel length...btw where did you see this device used? My thinking is its just a way of breaking up a long device into two smaller ones. Maybe for matching purposes or something like that.

cheers,
Aaron

Title: Re: Self-biased current mirror question
Post by Visjnoe on Mar 29^th, 2010, 10:32am

It is used for example in this paper:

Sinischalchi & al, "A CMOS ADSL codec for central office applications", JSSC March 2001.
They explicitly show that both devices in the stack are of different type in their implementation. It's this paper that got me thinking...

Regards

Title: Re: Self-biased current mirror question
Post by subgold on Mar 29^th, 2010, 12:50pm

Visjnoe wrote on Mar 29^th, 2010, 10:32am:

i have no access to that paper at the moment, but i think although different types of device could make the realization easier, it is still possible with the same type. the upper one has to be in very deep weak inversion while the lower one is sized in very strong inversion. you can even tweak the Vt a little bit by biasing the bulk.

Title: Re: Self-biased current mirror question
Post by tzg6sa on Mar 29^th, 2010, 2:24pm

Here is a topic addressing the same/similar issue:
http://www.designers-guide.org/Forum/YaBB.pl?num=1162979112/0

Title: Re: Self-biased current mirror question
Post by sos on Mar 30^th, 2010, 8:04am

Visjnoe wrote on Mar 27^th, 2010, 6:34am:

......
When you use devices with the same VT, you can easily see that the bottom transistor will always reside in the linear region.
OK, this is a form of 'degeneration', but linearity is usually not so important when it comes to biasing current mirrors.
Also, when I perform handcalculations on the structure with the bottom transistor in the linear region, I find you don't gain
much in terms of output impedance.

However, when you use a low-VT device in combination with a high-VT device, you can size this structure as a cascoded current mirror with the well-known 'gm*ro1*ro2' output impedance effect.

The idea is that you specifically do not use the same size devices. Make the W/L of the upper device larger than that of the lower device. Make it large enough to provide headroom for the lower device so it is not in the linear region. This way you cascode the lower device without having to provide a special reference voltage. This is about the best you can do for a cascode that does not require higher supply voltage.

Steve

Title: Re: Self-biased current mirror question
Post by Visjnoe on Mar 30^th, 2010, 10:35am

You cannot -through sizing- keep the lower device from being in the linear region.

The upper device requires at least VT as gate-source voltage to be on, therefore the drain-source voltage over the lower devices is lower than VGS-VT, thus it resides in the linear region.

Regards

Title: Re: Self-biased current mirror question
Post by RobG on Mar 30^th, 2010, 7:53pm

Visjnoe wrote on Mar 30^th, 2010, 10:35am:

Actually, what you do is operate the top device in weak inversion so its Vgs < Vt. Alternatively you can bias the bulk, or use a different threshold device (like a "natural" NMOS) to keep the Vgs less than the Vt of the bottom device. I've seen circuit referred to as a self cascode.

I've grown wary of using this structure as a self cascode. The old CMOS models didn't handle it correctly and the results were different than I expected... and as a practical matter it is hard to get the bottom device far enough out of the linear region to where it really gives a big increase in output Z.

Title: Re: Self-biased current mirror question
Post by Visjnoe on Mar 31^st, 2010, 3:26am

Dear Rob,

Thanks for the feedback.

From handcalculcations on this basic structure, I can indeed see that you don't gain much in terms of output impedance. Therefore, a true cascoded current mirror (with both devices in saturation) looks like the better option (obtain gm*ro1*ro2 as output impedance).

Regards

Title: Re: Self-biased current mirror question
Post by RobG on Mar 31^st, 2010, 9:35am

Visjnoe wrote on Mar 31^st, 2010, 3:26am:

In theory if the top device is deep enough into weak inversion both devices will be in saturation. However, it has to be pretty deep weak inversion. There is a transition zone between linear and saturation with an relatively low impedance even though the simulation says its in saturation. It seems like you need 200 mV or more of Vds on the bottom device before you get the full r_o impedance.

If you use a low-vt device the bottom device is definitely in saturation, but if that device's Vt is less than zero you can't diode connect the one side of the mirror which makes it pretty useless!

As a practical matter, the number of applications where this mirror works is pretty small. Mostly weak inversion applications.

rg

Title: Re: Self-biased current mirror question
Post by love_analog on Apr 22^nd, 2010, 4:32pm

I guess this is an old thread but I found it interesting.

I have seen it used some 65nm etc type of technologies to increase gds of the device. Longer L doesn't really get you larger impedence (because of halo implant etc). So people take short L devices and put them in series to get larger impedence.