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Design >> Analog Design >> common mode of CML latch
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Message started by casual on Mar 27^th, 2010, 7:30am

Title: common mode of CML latch
Post by casual on Mar 27^th, 2010, 7:30am

to design a high-speed CML latch (classical one), does the common-mode of the clock must be lower than data input common mode? (so that it can be completely turn off)

It works fine if the clock and data input common mode are same.

Pls advise and comment.

Title: Re: common mode of CML latch
Post by panditabupesh on Mar 27^th, 2010, 3:32pm

Having lower input common mode means an extended swing at the output before the input transistor goes into triode region.

Bupesh

Title: Re: common mode of CML latch
Post by casual on Mar 28^th, 2010, 7:07am

The data common-mode is definitely near to vdd (vdd-swing/2).
I mean the clk input common mode. Shall it be same or much lower?

Title: Re: common mode of CML latch
Post by love_analog on Apr 7^th, 2010, 9:30pm

Assume the input to the data has CM=dx
Assume input to clock has CM=cx

Now if all the gates are at their common-mode, then we get the drain of the clock transistors as having a voltage = dx-vgs
whereas the clock transistors will have Vg=cx

So ideally you'd like clock ones to have cx<dx.

Title: Re: common mode of CML latch
Post by casual on May 4^th, 2010, 7:04pm

Any problem if dx=cx? where the clk transistors are in triode mode since latch is a nonlinear circuit

Title: Re: common mode of CML latch
Post by love_analog on May 5^th, 2010, 12:39pm

Simulate it. I think you will see extra glitches in your output. But maybe you are okay with it.