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Design Languages >> Verilog-AMS >> Verilog-A model for ADC
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Message started by lyko on Apr 12^th, 2010, 2:06am

Title: Verilog-A model for ADC
Post by lyko on Apr 12^th, 2010, 2:06am

Dear All
It is posible to get a model of ADC using Verilog(including delay from clk to outputs and an input voltage to 10 or more bits binary numbers.) Why is Verilog-A usually used in modelling ADC?
I am a beginner in Verilog-A. :-[
Thanks for your attention.
Lyko

Title: Re: Verilog-A model for ADC
Post by Geoffrey_Coram on Apr 13^th, 2010, 10:51am

lyko wrote on Apr 12^th, 2010, 2:06am:

Why is Verilog-A usually used in modelling ADC?

How would you think to represent the Analog input in (digital) Verilog?

Generally, the Analog input signal varies continuously (ramps up or down or something); it's not event-driven like (digital) Verilog.

Title: Re: Verilog-A model for ADC
Post by lyko on Apr 13^th, 2010, 7:42pm

Thanks. I heard that some IP vendor offered verilog model of ADC for verification. That's why I asked.
But I would prefer to use verilog-A for modelling based on your reply.

Title: Re: Verilog-A model for ADC
Post by Marq Kole on Apr 14^th, 2010, 1:03am

There are a few simple examples of ADCs in the Verilog-AMS standard. Also, if you have access to the Cadence tooling there are examples in the ahdlLib library delivered with Cadence IC and/or MMSIM.

Cheers,
Marq