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Design Languages >> Verilog-AMS >> Probing port voltages of verilogA block from ams testbench
https://designers-guide.org/forum/YaBB.pl?num=1271176372

Message started by Dan Clement on Apr 13^th, 2010, 9:32am

Title: Probing port voltages of verilogA block from ams testbench
Post by Dan Clement on Apr 13^th, 2010, 9:32am

Dear Forum:

I am in need of some guidance... I think I have figured out that what I am doing is not possible but I am hoping the forum can help provide some alternatives to accomplish the goal and some explanations of why it isn't possible.

I will need to give some background first:

I am running top level simulation verification using cadence ams through the analog design environment gui. My schematic with config view has two instances, STIM for stimulus and DUT for device under test. Inside of the DUT (top level chip of course) is a bias block with a feedback connection. The bias block is represented by a verilogA model that is already known to match the real schematic.

The problem that I have is trying to figure out how to probe the input and output pin voltages of the bias block to verify the feedback connection is in the top level schematic as required.

i.e. compareValues(V(testbench.dut.bias.out), V(testbench.dut.bias.in), tolerance...); //note this is pseudo-code

Recall my stimulus is an ams block and the model is verilogA. When I try to access the potential (from the ams stimulus) of the pins (verilogA block), I get an error about attempting to modify defparam and that it is not allowed...

I've looked into the LRMs for ams and verilogA. From the ams LRM I found verbage that I believe says you can't do what I am trying to do.

First question: Why not? What is the technical limitation?

Second question: Why does the simulator think I'm trying to modify defparams?

Third question: What are some other ideas for verifying that the feedback wire is in the top level schematic?

Fourth question/comment: It seems that I will need some clever way to use wreals or $numtobits $bitstonum, is that correct? Based on my reading of the LRMs this seems to be the only practical way to do what I am trying to do...

Thanks in advance for helping me understand this better. I am new to ams and obviously have more to learn! :)

-Dan

FYI: I am using:
DFII: 5.10.41.500.6.132
NCVLOG: 08.20-s009
MMSIM: 7.0.1.136.isr12

Title: Re: Probing port voltages of verilogA block from ams testbench
Post by Geoffrey_Coram on Apr 13^th, 2010, 10:52am

Where were you trying to place this code?

compareValues(V(testbench.dut.bias.out), V(testbench.dut.bias.in), tolerance...);

I take it that it is not in the dut nor stim.

Title: Re: Probing port voltages of verilogA block from ams testbench
Post by Dan Clement on Apr 13^th, 2010, 11:20am

Hi Geoffrey,

The compareValues is a helper task function that gets included in the STIM instance so it becomes inline with the tests being performed in the STIM testbench.

Does that make sense?

Thanks,
Dan

Title: Re: Probing port voltages of verilogA block from ams testbench
Post by Geoffrey_Coram on Apr 14^th, 2010, 8:40am

Can you place it inside a module instead?

Title: Re: Probing port voltages of verilogA block from ams testbench
Post by Dan Clement on Apr 14^th, 2010, 11:03am

It is in a module, in the ams stimulus file...

Did I misunderstand?

Title: Re: Probing port voltages of verilogA block from ams testbench
Post by Geoffrey_Coram on Apr 15^th, 2010, 8:27am

Does compareValues end up inside an analog block?

What if you put
$strobe("out=%g, in=%g", V(testbench.dut.bias.out), V(testbench.dut.bias.in))

in the analog block? (This may tell you if there's a problem with the out-of-module references V(testbench.dut.bias.out), or whether it's a problem with compareValues.)

I'm not quite sure what you mean by "helper task function".

Title: Re: Probing port voltages of verilogA block from ams testbench
Post by Dan Clement on Apr 16^th, 2010, 5:52am

I am sure that the compareValues works properly because it is used many times in my chip verification simulations.

The only thing unique about when it doesn't work is that I am trying to probe the voltage of a port instead of a top level schematic wire.

The compareValues function does not end up in the analog block, only in the discrete/verilog block.

I like your idea of trying to do this from the analog block. That may provide some more clues.

Thanks,
Dan