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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> tackling noise in OPAMP : any preferred architecture ??? https://designers-guide.org/forum/YaBB.pl?num=1271388588 Message started by Dipankar on Apr 15th, 2010, 8:29pm |
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Title: tackling noise in OPAMP : any preferred architecture ??? Post by Dipankar on Apr 15th, 2010, 8:29pm Dear All, Can someone share some experience regarding low noise OPAMP design . Basic things I follow is 1 make gm of the differential pair higher compared to the load device 2. If possble use a little bigger device to lower the flicker. 3. use PMOS differential pair. 4. where possible use resistor load for the second stage. (I don't like to increase miller cap to improve noise (voltage) performance at the cost of BW or power. ) But is there any study or thumb rule regarding architecture selection - under same dc power consumption which one is noisier than other. |
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Title: Re: tackling noise in OPAMP : any preferred architecture ??? Post by Mayank on Apr 17th, 2010, 9:28pm A correction -- Make Gm/Id of the load device smaller than input one. QUESTION -- how will a pMOS input transistor reduce noise ?? addition -- you can filter Tail Current Source noise with a // cap or a series inductor. |
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Title: Re: tackling noise in OPAMP : any preferred architecture ??? Post by nobody on Apr 17th, 2010, 10:42pm Pmos input pairs are used for low flicker noise,I guess. |
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Title: Re: tackling noise in OPAMP : any preferred architecture ??? Post by analog_chip on Apr 19th, 2010, 3:34am Is there any provision for using BJT or let me know the maximum supply current that you are looking for from the architecture and also the input bias current. What is the noise value you are considering for design? |
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Title: Re: tackling noise in OPAMP : any preferred architecture ??? Post by Dipankar on Apr 19th, 2010, 9:11am No BJT available. spec : input referred noise ~ 6 nV / sqrt(Hz) @ 2MHz , total dc current ~ 300 uA, vdd = 1.8 , CL ~ 0.1- 0.2 p . GBW > 300 MHz , PM > 60. |
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Title: Re: tackling noise in OPAMP : any preferred architecture ??? Post by loose-electron on Apr 19th, 2010, 4:26pm Why don't yopu take a systematic approach and do a noise analysis of the device and find out what are the noise contributors? - Oh and one comment - a parallel capacitor on the tail current source? On the source itself kills you common mode rejection of the amplifier = bad thing. On the bias of the source is ok. |
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Title: Re: tackling noise in OPAMP : any preferred architecture ??? Post by Mayank on Apr 21st, 2010, 7:51am Hi, @ Jerry : Yes Sir, CMRR will degrade at higher frequencies...But if cap is chosen keeping in mind the CMRR / CMFB LoopGain BW, then it should not be a problem i guess. Anyways, A cap at Bias OR Passive RC filtering will bring down noise injection from Bias cktry...which is widely used now...But it wont bring down Noise injection from Tail Current Source. Also, can somebody explain wot "nobody" said :P & I Quote:
thanks, Mayank. |
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Title: Re: tackling noise in OPAMP : any preferred architecture ??? Post by thechopper on Apr 21st, 2010, 6:32pm Some additional comments/suggestions Dipankar wrote on Apr 15th, 2010, 8:29pm:
1. However, larger gm means larger BW, thus integrated noise is NOT improved...the only way is by increasing miller cap (at least for two stage amps) although you do not like it. 2. Chopp the amplifier so you get rid of the flicker 3. IF chopper is not possible then PMOS ok 4. Use resistor load for first stage, where noise is set. Use max possible tail current and minimum resistor load. Best Tosei |
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