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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> spectre's behavior depends on simulation time https://designers-guide.org/forum/YaBB.pl?num=1271403464 Message started by ayounis on Apr 16th, 2010, 12:37am |
Title: spectre's behavior depends on simulation time Post by ayounis on Apr 16th, 2010, 12:37am I am puzzled! I have a behavioral model of a pll that uses verilogA as well as regular models of different analogLib components (pwl, vdc, ...). I simulated this model in spectre and hspice. for short simulation time, say 10us, the output of the two simulators match, however, when I change the simulation time to 100us, spectre's output changes in the first 10us, while hspice output stays the same in the first 10us. I am confident that spectre is doing something strange (and incorrect) when I changed the simulation time. I have tried many accuracy settings for spectre and no luck so far! Anyone saw this behavior before? |
Title: Re: spectre's behavior depends on simulation time Post by ywguo on Apr 16th, 2010, 5:36am Hi ayounis, What's the strange behavior? What's your accuracy setting? What's the ref/output frequency of your PLL? Yawei |
Title: Re: spectre's behavior depends on simulation time Post by sheldon on Apr 16th, 2010, 6:20am Ayounis, Given the information provided, it is a little hard to make suggestions. I have simulated a lot of different PLLs with Spectre and there should not be an issue. The only thing that I can suggest is that there model may not be well-formed. In that case, it might help to set maxstep. Try setting maxstep so that the simulator takes a 2 points per period of the VCO and see what happens. Best Regards, Sheldon |
Title: Re: spectre's behavior depends on simulation time Post by ayounis on Apr 16th, 2010, 6:59am I have tried all accuracy settings that I know. Here is what I remember of them. Remember that there are two cases that I experimented with; case1 is the simulation that runs for 10us and case2 is the simulation that runs for 100us. I saw improper behavior for case2, when it is compared to case1 and also when it is compared to same setup but running hspice. hspice was consistent for the two time durations. a. From Cadence: 1. setting maxstep for case2 to be smaller or larger than that case1 did not seem to solve the problem. 2. I changed the "step" for case2 to be smaller/larger than that of case1. That did not solve the problem. 3. I tried the different integration methods, no luck. 4. I tried "conservative", "moderate" and "liberal", ... no luck. 5. Changed "reltol" to a much smaller value, no luck. 6. there might be other things that I also did but don't remember now. b. From command line: 1. I only changed "stop" in input.scs to go from case1 to case2 and I saw the problem. What I mean here is that all other simulator options in input.scs file remained the same, but spectre's behavior was different. 2. I tried different versions of spectre, no luck. Thats when I gave up and posted this issue! Ahmed |
Title: Re: spectre's behavior depends on simulation time Post by sheldon on Apr 16th, 2010, 7:57am A, Why don't you back to the beginning, the default setup and run the simulation and identify why the simulation results do not meet your expectation and then identify the the source of the improper behavior: - Does the VCO not lock? - Does the VCO lose lock? - Is the VCO flat line? - Is the VCO control voltage out of range? - Is the output of the PFD correct? - Is the Divider oscillating? - ...? Identify where in the loop is there an issue and use that information to tell you about where the issue is in the loop. Best Regards, Sheldon |
Title: Re: spectre's behavior depends on simulation time Post by ayounis on Apr 16th, 2010, 8:33am Thanks Sheldon, When I run the setup for 10us using spectre, I get what I expect. When I change the simulation time *only* from 10us to 100us and rerun, I get a totally different behavior of the control voltage. All blocks are working; vco is oscillating with the correct frequency, pfd is working as expected, but the in the first 10us of the simulation, I don't see the same behavior of the control voltage. i.e., the control voltage will look different when you set the stop to 10us and let the simulation finish, and when you set stop to 100us and then stop the simulation after 10us. Am I making sense here? Ahmed |
Title: Re: spectre's behavior depends on simulation time Post by ayounis on Apr 16th, 2010, 10:25am I found what the problem is. It is the transition function that I use. transition(val, Delay, TransTime, TransTime) If TransTime is passed as 0, spectre make the actual transition time a function of stop, however, it uses the actual value of TransTime if it is non zero. hspice will always use the actual valueof TransTime. I am not sure if this is intentional in spectre or not. Ahmed |
Title: Re: spectre's behavior depends on simulation time Post by Ken Kundert on Apr 19th, 2010, 12:49am The problem came when you specified 0 for a transition time. It makes no sense for the transition function to produce a zero duration transition as it causes a variety of numerical problems. So if you specify a 0 for a transition function, it will do its best to choose a reasonable non-zero value to use. Such behavior is required for every Verilog-A/MS simulator. How that default value is chosen is left up to the simulator, and choosing it as some fraction of the simulation interval is very natural as it scales with the problem. Bottom line, specify a non-zero transition time. |
Title: Re: spectre's behavior depends on simulation time Post by ayounis on Apr 20th, 2010, 7:16am Thanks Ken. I learned that the hard way! Ahmed |
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