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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> How to write a time amplifier? https://designers-guide.org/forum/YaBB.pl?num=1271645088 Message started by 5gougou on Apr 18th, 2010, 7:44pm |
Title: How to write a time amplifier? Post by 5gougou on Apr 18th, 2010, 7:44pm How to write a 2x time amplifier with Verilog-A? This is a model with two input signals with a time interval of T1, and two outputs with time interval 2*T1. Does anyone knows? Thanks very much~ :) |
Title: Re: How to write a time amplifier? Post by Marq Kole on Apr 19th, 2010, 2:01am What do you mean with a time interval? Is there a delay between the two signals or a phase difference? It is unclear to me what the circuit is supposed to do. Would it be possible to explain or to point to a site where such a function is explained. Marq |
Title: Re: How to write a time amplifier? Post by 5gougou on Apr 19th, 2010, 3:51am The time interval means a time delay between the two signals. This circuit is going to amplify that delay. Sorry for the unclear statement. Please contact if any further confusion. Or you may like to see that circuit in this file: http://www.staff.ncl.ac.uk/david.kinniment/Research/papers/ElectLett2002.PDF Thanks very much :) |
Title: Re: How to write a time amplifier? Post by Marq Kole on Apr 19th, 2010, 7:47am I would do something like this: Code:
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Title: Re: How to write a time amplifier? Post by 5gougou on Apr 22nd, 2010, 12:23am This is the very code I want. Thank you very much! Ruili :) |
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