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Design Languages >> Verilog-AMS >> syntax?
https://designers-guide.org/forum/YaBB.pl?num=1272049739

Message started by colorcircle on Apr 23^rd, 2010, 12:08pm

Title: syntax?
Post by colorcircle on Apr 23^rd, 2010, 12:08pm

Hii
does someone knows how to use clock in veriloga
i need to do the simulation by giving a frequency of 100hz
am new to this thing,so would be nice if someone tells

you can take my program as this(example)
`include "disciplines.vams"
module equation(y,x);
output y;
input x;
voltage x,y;
analog begin
V(y)<+V(x)
end
endmodule

i know theres no need for clock in above,,but just explain how i would write syntax,if i need to make simulation for above program with 100Hz clock,,the code for that..(at falling edge of clock)

thank you

Title: Re: syntax?
Post by Geoffrey_Coram on Apr 26^th, 2010, 4:41am

Do you want to generate the clock within the module, or have an external clock that comes in through another port?

Did you look through the Functional Models on the Verilog-AMS page (click "Verilog-AMS" in the header bar of this web site, between Forum and Analysis)?