The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Latch D->Latch T
https://designers-guide.org/forum/YaBB.pl?num=1272225552

Message started by Daniel Minan on Apr 25^th, 2010, 12:59pm

Title: Latch D->Latch T
Post by Daniel Minan on Apr 25^th, 2010, 12:59pm

I want to make a toggle latch from D latch using only data flow only:

module latcht(
input T,
output Led
);

wire d, c, qn;
//1'b0;
assign c = 1'b1;
assign d = q^T;
latchd U1( d, c, q, qn);

endmodule

module latchd(
input D,
input C,
output Q,
output Qn
);

/*assign Q = ((C==1'b1&&D==1'b0)? 1'b0 :((C==1'b1 && D==1'b1)?1'b1: Q));
assign Qn = ~Q;*/

endmodule

But when i tested the logic of the Led, it hold at z state all the time

Sorry for my poor english

Title: Re: Latch D->Latch T
Post by boe on Apr 26^th, 2010, 6:28am

Daniel Minan,
You need to force a defined initial state, e.g. by adding a reset.
Without that your circuit is likely to remain in X (not Z) initial state.

B O E