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Simulators >> Circuit Simulators >> MLIN simulation question in RFDE
https://designers-guide.org/forum/YaBB.pl?num=1272383469

Message started by liletian on Apr 27th, 2010, 8:51am

Title: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 8:51am

 Hi Guys
 I am simulating a filter using transmission line. I use MLIN for the transmission line in ADS. The software reports the following errors.
Can anyone suggest how to fix it? It seems to complain I did not give the model for substrate which I specified as Msub1. Do I need to give a seperate substrate file? If so, can anyone give me a sample Msub1 file.
 I will greatly appreciate it.

 hpeesofsim (*) 350.500 Feb 18 2009 (built: 02/18/09 23:50:00)
Copyright Agilent Technologies, 1989-2008.

Warning detected by hpeesofsim during netlist flattening.
   Cannot find substrate `MSub1'.

Error detected by hpeesofsim during netlist flattening.
   `I4':  Expected a substrate model for parameter `Subst'.


Flushing data (please wait) ...

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 27th, 2010, 9:29am

I can't find out any design issue in your post.

Your questions are no more than very easy issues regarding usage of very specific vendor's tool.


liletian wrote on Apr 27th, 2010, 8:51am:
I use MLIN for the transmission line in ADS.
.....
It seems to complain I did not give the model for substrate which I specified as Msub1.
See http://www.designers-guide.org/Forum/YaBB.pl?num=1265012932

http://edocs.soco.agilent.com/display/ads2009/MSUB+%28Microstrip+Substrate%29
This is also available in "adsLib" of Agilent RFDE.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 10:10am

 Hi pancho
 Thanks for your comments, I did find there is a component in adsLib called MSUB. However, can you specify how I can solve the problem? Any suggestions? Most of the adsLib components work fine so far except Mlin.
 I put a MSUB into the schematics and it still reported the same error.
 Thank you

pancho_hideboo wrote on Apr 27th, 2010, 9:29am:
I can't find out any design issue in your post.

Your questions are no more than very easy issues regarding usage of very specific vendor's tool.


liletian wrote on Apr 27th, 2010, 8:51am:
I use MLIN for the transmission line in ADS.
.....
It seems to complain I did not give the model for substrate which I specified as Msub1.
See http://www.designers-guide.org/Forum/YaBB.pl?num=1265012932

http://edocs.soco.agilent.com/display/ads2009/MSUB+%28Microstrip+Substrate%29
This is also available in "adsLib" of Agilent RFDE.


Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 27th, 2010, 10:13am

Show me schematic and netlist.

I think you will fail in creating netlist because I think there are many mistakes in your schematics.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 10:15am

 I attached the schematics, I did not find netlist file in the directory.

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 27th, 2010, 10:17am

No. this is not substrate definition component.


liletian wrote on Apr 27th, 2010, 10:15am:
I did not find netlist file in the directory.
Do you understand simulation launch mechanithm in RFDE ?
See http://www.designers-guide.org/Forum/YaBB.pl?num=1265391679

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 10:19am

could you please tell me how to define it?
thanks

pancho_hideboo wrote on Apr 27th, 2010, 10:17am:
No. this is not substrate definition component.


Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 27th, 2010, 10:23am

Show me netlist.


liletian wrote on Apr 27th, 2010, 10:19am:
could you please tell me how to define it?
Simply place substrate definition component in schematic.
In your schematic, there is no one.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 10:28am


pancho_hideboo wrote on Apr 27th, 2010, 10:23am:
Show me netlist.


liletian wrote on Apr 27th, 2010, 10:19am:
could you please tell me how to define it?
Simply place substrate definition component in schematic.
In your schematic, there is no one.

I am sorry, it might be dummy question. But can you tell me how to place substrate definition component in schematic? The closest component I found in adsLib is MSUB. Please give details, thank you so much!

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 27th, 2010, 10:31am

In your schematic, there is no "adsLib/MSUB".

There are "MLIN", "TLIN", "Term", "analogLib/cap", "analogLib/res" and "analogLib/gnd".

Again see http://www.designers-guide.org/Forum/YaBB.pl?num=1265012932

From your all previous posts, I think you can't understand ADS and RFDE at all.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 10:36am

yes, I mixed the components from analogLib and adsLib. Thank you for your reply. I will have a look on the post.
Why do you think I do not understand RFDE at all.
I think RFDE is a software to use ADS simulator and library. And at the same, use cadence to layout.
 Are there more deep understanding on RFDE?
 Thank you again

pancho_hideboo wrote on Apr 27th, 2010, 10:31am:
In your schematic, there is no "adsLib/MSUB".

There are "MLIN", "TLIN", "Term", "analogLib/cap", "analogLib/res" and "analogLib/gnd".

Again see http://www.designers-guide.org/Forum/YaBB.pl?num=1265012932

From your all previous posts, I think you can't understand ADS and RFDE at all.


Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 27th, 2010, 10:38am


liletian wrote on Apr 27th, 2010, 10:36am:
yes, I mixed the components from analogLib and adsLib.
Mixture of "analogLib" and "adsLib" is no problem.


liletian wrote on Apr 27th, 2010, 10:36am:
Why do you think I do not understand RFDE at all.
See all your previous posts in both "this forum" and "http://www.edaboard.com/forum63.html".



Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 10:44am

It is might be true I did not know ADS too much.
I modified the schematics, now it reported new errors.
Here is the error.
Any suggestions?

hpeesofsim (*) 350.500 Feb 18 2009 (built: 02/18/09 23:50:00)
Copyright Agilent Technologies, 1989-2008.

Error detected by hpeesofsim during netlist parsing.
   ADS-syntax parser error in `input.ckt', line 6:
       syntax error

Flushing data (please wait) ...

hpeesofsim terminated due to an error.
ds2psf_exe--ERROR: Cannot access file /home/hehe/simulation/test_TL_filter/ADSsim/schematic/netlist/data.ds.
\nds2psf was unsuccessful.  PSF files are not available for this simulation.


pancho_hideboo wrote on Apr 27th, 2010, 10:38am:

liletian wrote on Apr 27th, 2010, 10:36am:
yes, I mixed the components from analogLib and adsLib.
Mixture of "analogLib" and "adsLib" is no problem.


liletian wrote on Apr 27th, 2010, 10:36am:
Why do you think I do not understand RFDE at all.
See all your previous posts.


Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 27th, 2010, 10:48am

There is a substrate definition component in this schematic(http://www.designers-guide.org/Forum/Attachments/Screenshot-3_001.png).


liletian wrote on Apr 27th, 2010, 10:44am:
Error detected by hpeesofsim during netlist parsing.
   ADS-syntax parser error in `input.ckt', line 6:
       syntax error
Show me netlist.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 10:52am


pancho_hideboo wrote on Apr 27th, 2010, 10:48am:
There is a substrate definition component in this schematic.
Did you understand there is no one in previous your schemtic ?


liletian wrote on Apr 27th, 2010, 10:44am:
Error detected by hpeesofsim during netlist parsing.
   ADS-syntax parser error in `input.ckt', line 6:
       syntax error
Show me netlist.

 Now I understood there was no substrate in my previous post. I did not realize I need to put it in the schematics. First time to have this question.
thank you!
I did not find netlist file in my directory. I attached the totally directory file.
thank you

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 27th, 2010, 11:00am


pancho_hideboo wrote on Apr 27th, 2010, 10:58am:
Later I will do netlisting of your schematic("test_TL_filter_tar.gz").

thank you, I am looking forward to your reply.
;D

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 28th, 2010, 7:40am


liletian wrote on Apr 27th, 2010, 11:00am:

pancho_hideboo wrote on Apr 27th, 2010, 10:58am:
Later I will do netlisting of your schematic("test_TL_filter_tar.gz").

thank you, I am looking forward to your reply.
;D

 hi pancho
 Did you have a look on the file? What is the problem?
 Thank you,
 B

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 28th, 2010, 8:16am


liletian wrote on Apr 27th, 2010, 10:44am:
Error detected by hpeesofsim during netlist parsing.
   ADS-syntax parser error in `input.ckt', line 6:
       syntax error
(1) Don't enclose MSub1 for "Subst" parameters of "MLIN" with double quotations if you use RFDE(ADSsim).
This is a syntax error in the above.
See schematic for ADSsim in attached figure.
On the other hand, you can enclose with double quotations if you use Agilent GoldenGate.

(2) Callback skill code for netlisting of "adsLib/MSUB" is corrupted due to some reason.
My RFDE is CDBA version of RFDE2008Update2.
As far as CDBA version of RFDE2008Update2, callback skill code for netlisting of "MSUB" can't work.
Try to use OpenAccess version, for exaple, OpenAccess version of RFDE2009 which is a final version of RFDE.

(3) As workaround, don't place "adsLib/MSUB" in schematic.
Instead include netlist scratch for "MSUB".
It is easily available in ADS native environment.

(4) Use Agilent GoldenGate instead of Agilent RFDE.


Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 28th, 2010, 8:29am

The followings are netlist sets for RFDE(ADSsim).

"test_TL_filter.ads"
Quote:
simulator lang=ads
Options ResourceUsage=yes Verbose=yes UseNutmegFormat=no TopDesignName="data"

; Generated by: DFII version 5.10.41.500.5.98 (using OASIS direct)

#include "~/RFDE/msub1.ads"

MLIN2:I4 net06 net7 Subst="MSub1" W=250.00u L=5m Wall1=1e+30 Wall2=1e+30 Mod=1

simulator lang=spectre
PORT1 (net06 0) port r=50 num=1 type=dc
PORT2 (net7 0) port r=10M num=2 type=dc
C0 (net7 0) capacitor c=100.0f

simulator lang=ads
Options:Options1 Temp=25.0 Tnom=27 TopologyCheck=yes GiveAllWarnings=yes MaxWarnings=10

S_Param:SP1 SweepVar="freq" SweepPlan="SP1_stim" CalcS=yes StatusLevel=2 \
   CalcNoise=no OutputPlan[1]="GlobalOutputPlan" OutputPlan[2]="GlobalInhibitPlan"

SweepPlan:SP1_stim Sort=yes Start=1k Stop=10G Dec=21

OutputPlan:GlobalOutputPlan Type="Output" UseBuiltinRule=no \
   OverrideInhibitRule=no UseNodeNestLevel=yes NodeNestLevel=2 \
   UseCurrentNestLevel=yes CurrentNestLevel=999 \
   UseDeviceCurrentNestLevel=no

OutputPlan:GlobalInhibitPlan Type="Inhibit" UseBuiltinRule=no \
   OverrideInhibitRule=no NodeRegExpr[1]="\.net[0-9]+$|^net[0-9]+$"

mapping {
 pinMapping {
   capacitor 1:"PLUS" 2:"MINUS"
   port 1:"PLUS" 2:"MINUS"
   MLIN2 1:"P1" 2:"P2"
 }
}


"msub1.ads"
Quote:
simulator lang=ads
model MSub1 MSUB H=10.0u Er=9.6 Mur=1 Cond=1e+50 Hu=1e+36 T=0 TanD=0 Rough=0

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 28th, 2010, 8:36am

The following is a netlist for Agilent GoldenGate.

"test_TL_filter_GG.scs"
Quote:
// Generated for: spectre
// Generated on: Apr 28 15:40:05 2010
// Design library name: My_RFDE_Test
// Design cell name: test_TL_filter_GG
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: My_RFDE_Test
// Cell name: test_TL_filter_GG
// View name: schematic

MSub1 MSUB H=10.0u Er=9.6 Mur=1 Cond=1e+50 Hu=1e+36 T=0 TanD=0 Rough=0

I4 (net06 net7) MLIN Subst="MSub1" W=250.00u L=5m Wall1=1e+30 Wall2=1e+30 Mod=Kirschning

PORT1 (net06 0) port r=50 num=1 type=dc
PORT2 (net7 0) port r=10M num=2 type=dc
C0 (net7 0) capacitor c=100.0f


Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 28th, 2010, 8:53am

(3) As workaround, don't place "adsLib/MSUB" in schematic.
Instead include netlist scratch for "MSUB".
It is easily available in ADS native environment.
How to do the netlist? It looks like RFDE does not generate the netlist for me.

(4) Use Agilent GoldenGate.
I rarely use GoldenGate and just give it a try. It reported the same errors.



pancho_hideboo wrote on Apr 28th, 2010, 8:29am:
The followings are netlist sets for RFDE(ADSsim).

"test_TL_filter.ads"
Quote:
simulator lang=ads
Options ResourceUsage=yes Verbose=yes UseNutmegFormat=no TopDesignName="data"

; Generated by: DFII version 5.10.41.500.5.98 (using OASIS direct)

#include "~/RFDE/msub1.ads"

MLIN2:I4 net06 net7 Subst="MSub1" W=250.00u L=5m Wall1=1e+30 Wall2=1e+30 Mod=1

simulator lang=spectre
PORT1 (net06 0) port r=50 num=1 type=dc
PORT2 (net7 0) port r=10M num=2 type=dc
C0 (net7 0) capacitor c=100.0f

simulator lang=ads
Options:Options1 Temp=25.0 Tnom=27 TopologyCheck=yes GiveAllWarnings=yes MaxWarnings=10

S_Param:SP1 SweepVar="freq" SweepPlan="SP1_stim" CalcS=yes StatusLevel=2 \
   CalcNoise=no OutputPlan[1]="GlobalOutputPlan" OutputPlan[2]="GlobalInhibitPlan"

SweepPlan:SP1_stim Sort=yes Start=1k Stop=10G Dec=21

OutputPlan:GlobalOutputPlan Type="Output" UseBuiltinRule=no \
   OverrideInhibitRule=no UseNodeNestLevel=yes NodeNestLevel=2 \
   UseCurrentNestLevel=yes CurrentNestLevel=999 \
   UseDeviceCurrentNestLevel=no

OutputPlan:GlobalInhibitPlan Type="Inhibit" UseBuiltinRule=no \
   OverrideInhibitRule=no NodeRegExpr[1]="\.net[0-9]+$|^net[0-9]+$"

mapping {
 pinMapping {
   capacitor 1:"PLUS" 2:"MINUS"
   port 1:"PLUS" 2:"MINUS"
   MLIN2 1:"P1" 2:"P2"
 }
}


"msub1.ads"[quote]simulator lang=ads
model MSub1 MSUB H=10.0u Er=9.6 Mur=1 Cond=1e+50 Hu=1e+36 T=0 TanD=0 Rough=0
[/quote]

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 28th, 2010, 8:55am


liletian wrote on Apr 28th, 2010, 8:53am:
I rarely use GoldenGate and just give it a try.
It reported the same errors.
Use "adsLib" for GoldenGate not for RFDE.



liletian wrote on Apr 28th, 2010, 8:53am:
How to do the netlist? It looks like RFDE does not generate the netlist for me.
It is same as Cadence spectre's netlisting in Cadence ADE.
Do you understand Cadence ADE ?

About netlisting in ADS native environment, see http://www.designers-guide.org/Forum/YaBB.pl?num=1265191125/7#7


Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 28th, 2010, 8:59am

how to use this file?
can you please give me the totally directory of the RFDE ADS, so I can have a look?
thanks

pancho_hideboo wrote on Apr 28th, 2010, 8:29am:
The followings are netlist sets for RFDE(ADSsim).

"test_TL_filter.ads"
Quote:
simulator lang=ads
Options ResourceUsage=yes Verbose=yes UseNutmegFormat=no TopDesignName="data"

; Generated by: DFII version 5.10.41.500.5.98 (using OASIS direct)

#include "~/RFDE/msub1.ads"

MLIN2:I4 net06 net7 Subst="MSub1" W=250.00u L=5m Wall1=1e+30 Wall2=1e+30 Mod=1

simulator lang=spectre
PORT1 (net06 0) port r=50 num=1 type=dc
PORT2 (net7 0) port r=10M num=2 type=dc
C0 (net7 0) capacitor c=100.0f

simulator lang=ads
Options:Options1 Temp=25.0 Tnom=27 TopologyCheck=yes GiveAllWarnings=yes MaxWarnings=10

S_Param:SP1 SweepVar="freq" SweepPlan="SP1_stim" CalcS=yes StatusLevel=2 \
   CalcNoise=no OutputPlan[1]="GlobalOutputPlan" OutputPlan[2]="GlobalInhibitPlan"

SweepPlan:SP1_stim Sort=yes Start=1k Stop=10G Dec=21

OutputPlan:GlobalOutputPlan Type="Output" UseBuiltinRule=no \
   OverrideInhibitRule=no UseNodeNestLevel=yes NodeNestLevel=2 \
   UseCurrentNestLevel=yes CurrentNestLevel=999 \
   UseDeviceCurrentNestLevel=no

OutputPlan:GlobalInhibitPlan Type="Inhibit" UseBuiltinRule=no \
   OverrideInhibitRule=no NodeRegExpr[1]="\.net[0-9]+$|^net[0-9]+$"

mapping {
 pinMapping {
   capacitor 1:"PLUS" 2:"MINUS"
   port 1:"PLUS" 2:"MINUS"
   MLIN2 1:"P1" 2:"P2"
 }
}


"msub1.ads"[quote]simulator lang=ads
model MSub1 MSUB H=10.0u Er=9.6 Mur=1 Cond=1e+50 Hu=1e+36 T=0 TanD=0 Rough=0
[/quote]

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 28th, 2010, 9:00am

Read all documenations of Agilent RFDE and Cadence ADE.


liletian wrote on Apr 28th, 2010, 8:59am:
how to use this file?
Include "msub1.ads" just same as transistor model file.

Again do you understand Cadence ADE ?

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 28th, 2010, 9:01am

My understanding is Goldsden gate is only a simulator under RFDE. Again, I do not know much on Golden Gate.


pancho_hideboo wrote on Apr 28th, 2010, 8:55am:

liletian wrote on Apr 28th, 2010, 8:53am:
I rarely use GoldenGate and just give it a try.
It reported the same errors.
Use "adsLib" for GoldenGate not for RFDE.



liletian wrote on Apr 28th, 2010, 8:53am:
How to do the netlist? It looks like RFDE does not generate the netlist for me.
It is same as Cadence spectre's netlisting in Cadence ADE.
Do you understand Cadence ADE ?


Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 28th, 2010, 9:03am


pancho_hideboo wrote on Apr 28th, 2010, 8:55am:

liletian wrote on Apr 28th, 2010, 8:53am:
I rarely use GoldenGate and just give it a try.
It reported the same errors.
Use "adsLib" for GoldenGate not for RFDE.



liletian wrote on Apr 28th, 2010, 8:53am:
How to do the netlist? It looks like RFDE does not generate the netlist for me.
It is same as Cadence spectre's netlisting in Cadence ADE.
Do you understand Cadence ADE ?

 no, I do not know how to do it. can you tell me how to use it?
 Thanks

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 28th, 2010, 9:03am


liletian wrote on Apr 28th, 2010, 9:01am:
My understanding is Goldsden gate is only a simulator under RFDE.
Not correct.
http://www.designers-guide.org/Forum/YaBB.pl?num=1268404959/7#7

I'm not kind and patient enough for answering such too basic questions.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 28th, 2010, 9:18am


pancho_hideboo wrote on Apr 28th, 2010, 9:03am:

liletian wrote on Apr 28th, 2010, 9:01am:
My understanding is Goldsden gate is only a simulator under RFDE.
Not correct.
http://www.designers-guide.org/Forum/YaBB.pl?num=1268404959/7#7

I'm not kind and patient enough for answering such too basic questions.

It is fine. I do not really need to know what golden Gate is?
If you can tell me how to use the netlist you showed to me in ADS, I will greatly appreciate your help.
Otherwise, thank you anyway for your help.

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 28th, 2010, 9:23am


liletian wrote on Apr 28th, 2010, 9:18am:
It is fine. I do not really need to know what golden Gate is?
I don't think you can manage to use Agilent GoldenGate, if I judge from all your previous posts in both "this forum" and "http://www.edaboard.com/forum63.html".


liletian wrote on Apr 28th, 2010, 9:18am:
If you can tell me how to use the netlist you showed to me in ADS, I will greatly appreciate your help.
Again see http://www.designers-guide.org/Forum/YaBB.pl?num=1272383469/23#23.

Simply include "msub1.ads" just same as transistor model file including when you use Spectre in Cadence ADE.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 28th, 2010, 9:49am


pancho_hideboo wrote on Apr 28th, 2010, 9:23am:

liletian wrote on Apr 28th, 2010, 9:18am:
It is fine. I do not really need to know what golden Gate is?
I don't think you can manage to use Agilent GoldenGate, if I judge from all your previous posts in both "this forum" and "http://www.edaboard.com/forum63.html".


liletian wrote on Apr 28th, 2010, 9:18am:
If you can tell me how to use the netlist you showed to me in ADS, I will greatly appreciate your help.
Again see http://www.designers-guide.org/Forum/YaBB.pl?num=1272383469/23#23.

Simply include "msub1.ads" just same as transistor model file including when you use Spectre in Cadence ADE.

whatever you say, thank you for your help. I finally got it to work.
Thanks a lot!


Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on Apr 29th, 2010, 1:37am


liletian wrote on Apr 27th, 2010, 10:52am:
I did not find netlist file in my directory. I attached the totally directory file.
What do you mean by "totally directory file".
Your directory is no more than "cell view" of "test_TL_filter" in your "design library" of "test" not "total directory".

Again do you understand directory structure of data created in Cadence DFII and Cadence ADE ?


liletian wrote on Apr 28th, 2010, 8:59am:
can you please give me the totally directory of the RFDE ADS, so I can have a look?
I can't understand what you mean by "RFDE ADS".

Directory structure of RFDE is basically same as Cadence ADE.
But directory structure of ADS project is different from RFDE.

In ADS, project directory includes both design library and simulation data directory.
On the other hand, in RFDE, project directory means simulation data directory which is different from design library.

In RFDE, total directory means design library, custom reference library, simulation directory(project directory) and analysis state directory.
"cell view" directory is never "total directory" in any meaning.

In ADS, total directory mean one project directory if no other project directory is included.


liletian wrote on Apr 27th, 2010, 10:36am:
Why do you think I do not understand RFDE at all.
I can't understand why you can say you understand RFDE.

Again surely read documentations of Cadence ADE and Agilent ADS and RFDE.

Title: Re: MLIN simulation question in RFDE
Post by liletian on Apr 29th, 2010, 8:38am


pancho_hideboo wrote on Apr 29th, 2010, 1:37am:

liletian wrote on Apr 27th, 2010, 10:52am:
I did not find netlist file in my directory. I attached the totally directory file.
What do you mean by "totally directory file".
Your directory is no more than "cell view" of "test_TL_filter" in your "design library" of "test" not "total directory".

Again do you understand directory structure of data created in Cadence DFII and Cadence ADE ?

I did understand some of them after conversation with you. Maybe not all of them.
For example, I know how to generate netlist through Cadence ADE now. but not other ways.


liletian wrote on Apr 28th, 2010, 8:59am:
can you please give me the totally directory of the RFDE ADS, so I can have a look?
I can't understand what you mean by "RFDE ADS".

Directory structures of RFDE is basically same as Cadence ADE.
But directory structure of ADS project is different from RFDE.

In ADS, project directory includes both design library and simulation data directory.
On the other hand, in RFDE, project directory means simulation data directory which is different from design library.

I got this now. Thank you.
In RFDE, total directory means design library, custom reference library, simulation directory(project directory) and analysis state directory.
"cell view" directory is never "total directory" in any meaning.


In ADS, total directory mean one project directory if no other project directory is included.


liletian wrote on Apr 27th, 2010, 10:36am:
Why do you think I do not understand RFDE at all.
I can't understand why you can say you understand RFDE.

Again surely read documentations of Cadence ADE and Agilent ADS and RFDE.


Thank you!

Title: Re: MLIN simulation question in RFDE
Post by pancho_hideboo on May 6th, 2010, 2:42am

The following is a netlist for Agilent GoldenGate simulator.
As you can see, this netlist style is very different from Agilent ADSsim and Cadence Spectre.

"SP.gg.expanded.gg"
Quote:
network main
{
     variable:
     {
           sweep freq { is_design = 1, max = 10000000000, min = 1000, dec = 21 };
           numeric temp { nom = 25, is_design = 1 };
           numeric tnom { nom = 27, is_design = 1 };
     };
     element:
     {
           lumped c2 C0 (net7,\0) { c = 1e-13 };
           microstrip mlin I4 (net06,net7) { l = 0.005, sub = "MSub1", w = 0.00025, wall1 = 1e+30,
wall2 = 1e+30, dispersion = Kirschning };
           hbsrc spsin PORT1 (net06,\0) { r = 50, type = dc, num = 1 };
           hbsrc spsin PORT2 (net7,\0) { r = 10000000, type = dc, num = 2 };
     };
     data:
     {
           microstrip substrate MSub1 { h = 10.0u, er = 9.6, mur = 1, cond = 1e+50,
hu = 1e+36, t = 0, tand = 0, rgh = 0 };
     };
}

simulation SP
{
     variable:
     {
     };
     analysis:
     {
           s_parameter { scale = 1, temp = 25.0, tnom = 27.0, print_dc_state = 2,
collapse_dc_source = 0, iabstol = 1e-12, sweep_cont = 99, gmin = 1.0e-12, conv_err = 0.100000,
gcomp = 1.000000e-12, pivabs = 1e-50, pivrel = 1e-3, resistor_thresh = 1.000000e-03, big_capacitor = 1e-07,
max_signal_value = 1.000000e+13, print_inventory = 1, print_parameter = 0, print_variable = 1, print_perf = 1,
perf_nb_digit = 4, process_spare = 1, topology_check = 1, multithread = 1, undef_par_behavior = 1,
deprecated_par_behavior = 1, tr_max_iter = 20, integ_method = "gear", integ_order = 2, tran_predict_order = 1,
err_print = 2, use_estimate = 0, print_s_param = 0 };
     };
     probe:
     {
     };
     signal:
     {
           small_signal { nominal_freq = freq };
     };
     specification:
     {
           specification_variable { var = [ freq ] };
     };
     task:
     {
           nominal { };
     };
     info:
     {
           netlister { version = "GoldenGate-4.3.6", buildnumber = 2151, library = "My_RFDE_Test", cell = "test_TL_filter_GG",
view = "schematic" };
           ggparser { version = "4.3.6" };
     };
}

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