The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> N.O. Clock Gen for Pipelined ADCs
https://designers-guide.org/forum/YaBB.pl?num=1272559561

Message started by RobG on Apr 29^th, 2010, 9:46am

Title: N.O. Clock Gen for Pipelined ADCs
Post by RobG on Apr 29^th, 2010, 9:46am

I think I have heard every option on the proper way to build a N.O. clock generator for a pipelined ADC:
1) A single generator with all the buffers inside the loop
2) A generator for each stage
3) A generator with buffers outside of the loop (a bit dangerous because if the delays don't match you could get overlap)
4) A single clock gen positioned at the end of the pipeline (so the first stage gets the clocks slightly later than the last stage
5) A single clock gen positioned at the beginning of the pipelined so the first stage clocks before the other stages.

I'm sure there are others. What are your opinions on the subject?

rg

Title: Re: N.O. Clock Gen for Pipelined ADCs
Post by Ken Kundert on Apr 30^th, 2010, 1:56am

N. O. means non-overlapping?

Title: Re: N.O. Clock Gen for Pipelined ADCs
Post by RobG on Apr 30^th, 2010, 7:41am

Yes, non-overlapping. Sorry for the confusion.

Title: Re: N.O. Clock Gen for Pipelined ADCs
Post by vivkr on May 3^rd, 2010, 12:00am

I have also seen:

1. "digital" nonoverlap where the system clock is much faster than the ADC clock, and the N.O. is thus chosen as 1 clock phase or so; not as bad as you might think, especially since there are practically no variations in the N.O.

2. On a similar note, but for higher speed systems which had a DLL on-chip, one could similarly generate a N.O. Might look a little riskier if the N.O. phases are not routed symmetrically, but that's a risk you always have with every method.

Vivek