The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Circuit Simulators >> AGC loop stability simulation in Cadence
https://designers-guide.org/forum/YaBB.pl?num=1272653740

Message started by Ruritania on Apr 30th, 2010, 11:55am

Title: AGC loop stability simulation in Cadence
Post by Ruritania on Apr 30th, 2010, 11:55am

Hi,

I'm trying to use Spectre to simulate the loop stability of the AGC shown below.

Since the loop can only work properly when a signal (sine wave) is presented at vin, is there any particular way to simulate the loop stability in such cases?

I tried PSS+PSTB, but the outputs are just two flat lines (phase margin & gain margin), which does not make any sense.

Thanks.

Title: Re: AGC loop stability simulation in Cadence
Post by pancho_hideboo on Apr 30th, 2010, 11:52pm

PSTB is no more than PAC of sideband=0.
Where do you insert probe ?

Show me your netlist regarding signal(power) sources and PSS/PSTB statement.

http://www.designers-guide.org/Forum/YaBB.pl?num=1217939784
http://www.designers-guide.org/Forum/YaBB.pl?num=1265101150

Title: Re: AGC loop stability simulation in Cadence
Post by buddypoor on May 1st, 2010, 1:47am


Ruritania wrote on Apr 30th, 2010, 11:55am:
Hi,

I'm trying to use Spectre to simulate the loop stability of the AGC shown below.

Since the loop can only work properly when a signal (sine wave) is presented at vin, is there any particular way to simulate the loop stability in such cases?

I tried PSS+PSTB, but the outputs are just two flat lines (phase margin & gain margin), which does not make any sense.

Thanks.


Hi RURITANIA,

I do not use SPECTRE. However, some general comments are to be given - independent on the simulator engine used.
Since the AGC loop is inherently non-linear it must be linearized before the rules of linear circuit theory may be applied (loop gain, phase margin,...)
At first, what kind of voltage controlled amplifier are you using?
I suppose, it will be "linear-in-dB" , correct?
In this case, you have to use the log function to linearize with the result that input/output/reference signals now are in dBV.
At second, you have to realize that the circuit only responds to changes of the input signal. With this in mind you can create a linearized block diagram in the s-domain which leads to the following loop gain expression:
Loop gain AL=-Kd*Kc*Fd*Fr  with
Kd=Vref*2.3/20 in V/dB ;
Kc=Ko*20/2.3 in dB/V  (Ko=sensitivity of gain control in exp(Ko*Vcontrol) ;
Fd=transfer function of level detector
Fr=Transfer function of controller/filter (smoothing of control voltage)

This model applies only for an amplifier which is "linear-in-dB" . The model does NOT depend on the level of inpiut power, but the variations of the input signal are limited to app. +- 1.5 dB (validity of the linear model).
Hope this helps.
Good luck and regards.

Title: Re: AGC loop stability simulation in Cadence
Post by Ruritania on May 3rd, 2010, 7:56am


pancho_hideboo wrote on Apr 30th, 2010, 11:52pm:
PSTB is no more than PAC of sideband=0.
Where do you insert probe ?

Show me your netlist regarding signal(power) sources and PSS/PSTB statement.

http://www.designers-guide.org/Forum/YaBB.pl?num=1217939784
http://www.designers-guide.org/Forum/YaBB.pl?num=1265101150


Thanks for your reply.

I agree that PSTB is no more than PAC of SB=0, but is there any issue to run it with PSTB?

I inserted the probe btwn the loop filter and VGA control input (Vc, in the pix of my last post).

Thanks.


Title: Re: AGC loop stability simulation in Cadence
Post by Ruritania on May 3rd, 2010, 8:16am


buddypoor wrote on May 1st, 2010, 1:47am:
Hi RURITANIA,

I do not use SPECTRE. However, some general comments are to be given - independent on the simulator engine used.
Since the AGC loop is inherently non-linear it must be linearized before the rules of linear circuit theory may be applied (loop gain, phase margin,...)
At first, what kind of voltage controlled amplifier are you using?
I suppose, it will be "linear-in-dB" , correct?
In this case, you have to use the log function to linearize with the result that input/output/reference signals now are in dBV.
At second, you have to realize that the circuit only responds to changes of the input signal. With this in mind you can create a linearized block diagram in the s-domain which leads to the following loop gain expression:
Loop gain AL=-Kd*Kc*Fd*Fr  with
Kd=Vref*2.3/20 in V/dB ;
Kc=Ko*20/2.3 in dB/V  (Ko=sensitivity of gain control in exp(Ko*Vcontrol) ;
Fd=transfer function of level detector
Fr=Transfer function of controller/filter (smoothing of control voltage)

This model applies only for an amplifier which is "linear-in-dB" . The model does NOT depend on the level of inpiut power, but the variations of the input signal are limited to app. +- 1.5 dB (validity of the linear model).
Hope this helps.
Good luck and regards.


Hi buddypoor,

Thanks for your kind reply.

You raised a really important point that the previously mentioned stability theory can only be applied to the linearized circuits or components. Yes, my VGA is "linear-in-dB," and I did build the similar models in ahdl. But as you may know, the models are just rough estimates of the real circuits, and most likely you cannot include all of the poles/zeros in the models. Eventually you need to verify the stability in the REAL circuits.

Any comments on how to verify the stability of such loops with non-linear circuits in simulation?

Thanks.


Title: Re: AGC loop stability simulation in Cadence
Post by pancho_hideboo on May 3rd, 2010, 8:21am


Ruritania wrote on May 3rd, 2010, 7:56am:
I agree that PSTB is no more than PAC of SB=0, but is there any issue to run it with PSTB?
There is a problem in slave small signal analyses such as PAC, PXF, Pnoise, PSTB, PSP subjected to master PSS of Cadence Spectre for BSIM3 model use.

See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1200305082
http://www.designers-guide.org/Forum/YaBB.pl?num=1214897800
http://www.designers-guide.org/Forum/YaBB.pl?num=1265101150

Try to use other vendor's simulator or use newest Cadence Spectre(MMSIM).


Ruritania wrote on May 3rd, 2010, 8:16am:
Any comments on how to verify the stability of such loops with non-linear circuits in simulation?
See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1268385779
http://www.edaboard.com/ftopic272570.html
http://www.designers-guide.org/Forum/YaBB.pl?num=1243078889
http://www.designers-guide.org/Forum/YaBB.pl?num=1255834027

Title: Re: AGC loop stability simulation in Cadence
Post by buddypoor on May 3rd, 2010, 8:33am


Ruritania wrote on May 3rd, 2010, 8:16am:
........
But as you may know, the models are just rough estimates of the real circuits, and most likely you cannot include all of the poles/zeros in the models. Eventually you need to verify the stability in the REAL circuits.


What do you mean with "real circuits" ? Measurements rather than simulation?  For my opinion, only dominant poles/zeros are important for stability checks.

Title: Re: AGC loop stability simulation in Cadence
Post by Ruritania on May 3rd, 2010, 8:36am


pancho_hideboo wrote on May 3rd, 2010, 7:59am:

Ruritania wrote on May 3rd, 2010, 7:56am:
I agree that PSTB is no more than PAC of SB=0, but is there any issue to run it with PSTB?
There is a problem in slave small signal analyses such as PAC, PXF, Pnoise, PSTB, PSP subjected to master PSS of Cadence Spectre for BSIM3 model use.

See the followings.
http://www.designers-guide.org/Forum/YaBB.pl?num=1200305082
http://www.designers-guide.org/Forum/YaBB.pl?num=1214897800
http://www.designers-guide.org/Forum/YaBB.pl?num=1265101150

Try to use other vendor's simulator or use newest Cadence Spectre(MMSIM).


I just checked the log, the version is 6.2.1.390, 28 oct 2008. Does this version have the mentioned issue?

Thanks.

Title: Re: AGC loop stability simulation in Cadence
Post by pancho_hideboo on May 3rd, 2010, 8:38am


Ruritania wrote on May 3rd, 2010, 8:36am:
I just checked the log, the version is 6.2.1.390, 28 oct 2008. Does this version have the mentioned issue?
I don't know.
Expect answer from Cadence guys.

Title: Re: AGC loop stability simulation in Cadence
Post by Ruritania on May 3rd, 2010, 8:45am


[/quote]

What do you mean with "real circuits" ? Measurements rather than simulation?  For my opinion, only dominant poles/zeros are important for stability checks.
[/quote]

Hi buddypoor,

For "real circuits," I referred to the transistor level. What I meant is that, even if you successfully verified the loop stability in the linearized model level, you may still want to check the loop stability in the transistor level in the end of the day.

Thanks.

Title: Re: AGC loop stability simulation in Cadence
Post by buddypoor on May 4th, 2010, 12:13am


Ruritania wrote on May 3rd, 2010, 8:45am:
Hi buddypoor,
For "real circuits," I referred to the transistor level. What I meant is that, even if you successfully verified the loop stability in the linearized model level, you may still want to check the loop stability in the transistor level in the end of the day.
Thanks.


Of course, simulation can give you only a - more or less - rough estimate concerning circuit behaviour. But - that's a lot!
And, of course, you have to verify the results based on "real circuits". In particular, when you have simulated a linear model of a non-linear circuit. However, certain parameters (e.g. stability margins) are defined for linear systems only.

Title: Re: AGC loop stability simulation in Cadence
Post by love_analog on May 18th, 2010, 9:49pm

Buddypoor,
In your Origianl post, what is Kd and Kc.

Title: Re: AGC loop stability simulation in Cadence
Post by buddypoor on May 22nd, 2010, 8:22am


love_analog wrote on May 18th, 2010, 9:49pm:
Buddypoor,
In your Origianl post, what is Kd and Kc.


It is defined in my first posting May 1st.

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.