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Other CAD Tools >> Physical Verification, Extraction and Analysis >> two question for Cadence SOC Encounter design
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Message started by cnnnews on May 4^th, 2010, 5:28pm

Title: two question for Cadence SOC Encounter design
Post by cnnnews on May 4^th, 2010, 5:28pm

Hello,

Would you please answer me two questions?I will appreciate your help,
thank you!

1.when we use SOC encounter tools to Physical Design,how to make
wired-bound pads?where can we find out some examples to use
them.

2. when we use SOC encounter tools to design our chiip,how to create
and report the clock tree synthesis Specification file and how to get
*.ctstch file of tree clock synthesis?