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Design Languages >> Verilog-AMS >> random number generation
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Message started by rajdeep on May 7^th, 2010, 3:52am

Title: random number generation
Post by rajdeep on May 7^th, 2010, 3:52am

Hi All,

I was trying to use a $rdist_uniform to generate random numbers. The code portion is:

Code:

@(cross(V(clk) - fullscale/2.0,-1))
begin
th = $rdist_uniform(seed, lo, hi);
end
V(out) <+ th;

Seed has been defined as 1. I thought it would generate a random voltage at every negative edge of clk. But it does not do that!! Im running it using Cadence Spectre.
Any help?

Thanks!
Rajdeep

Title: Re: random number generation
Post by rajdeep on May 7^th, 2010, 4:28am

Hi all,

Sorry! I got the problem now! :-?
It was the seed variable. I made it hard coded!! I didnt realize this variable gets updated
internally!!

Rajdeep