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Design Languages >> Verilog-AMS >> verilogams simuation error
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Message started by liletian on May 10^th, 2010, 3:22pm

Title: verilogams simuation error
Post by liletian on May 10^th, 2010, 3:22pm

Hi Guys
I generated a diode through verilogAMS. However, when I simulate the diode, I saw the following error to even generate the netlist. Does anyone have idea what is going on here and how to fix it?
I attached the error screen.
Thank you

// VerilogA for test, diode, veriloga

`include "constants.vams"
`include "disciplines.vams"

module diode (a, c);
// saturation current (A)
parameter real is=10f from (0:inf);
// forward transit time (s)
parameter real tf=0 from [0:inf);
// zero-bias junction capacitance (F)
parameter real cjo=0 from [0:inf);
// built-in junction potential (V)
parameter real phi=0.7 exclude 0;
inout a, c;
electrical a, c;
branch (a, c) res, cap;
real qd;
analog begin
l(res) <+ is*(limexp(V(res)/$vt) -1);
qd = tf*l(res)-2*cjo*phi*sqrt(1-V(cap)/phi);
l(cap) <+ ddt(qd);
end
endmodule

Title: Re: verilogams simuation error
Post by Marq Kole on May 12^th, 2010, 7:42am

Just a stupid question perhaps, but did you do a "Check and Save" of your schematic view? You do need to instantiate the diode in a schematic view to be able to simulate it. Try to retrace the steps in creating the diode model and the instance of it in the schematic. Create a new, empty library as needed. Try to use the model from the ahdlLib (diode_sch) if you still run into problems.

You are using IC5 to see from the screen shot. Check that in the library for the diode you have a veriloga view (verilogams doesn't make sense for the model you have) and that the model text is contained in a file called veriloga.va (<library>/<cell>/veriloga/veriloga.va).

Cheers,
Marq

Title: Re: verilogams simuation error
Post by liletian on May 12^th, 2010, 8:02am

no, it does not work. I believe it is because of the software configuration.
thank you anyway

Marq Kole wrote on May 12^th, 2010, 7:42am: