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Modeling >> Behavioral Models >> opamp's slewrate model in verilog-a
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Message started by samiran on May 11^th, 2010, 12:07pm

Title: opamp's slewrate model in verilog-a
Post by samiran on May 11^th, 2010, 12:07pm

Hi all,

I require a simplistic veriloga model of opamp in which I need to take care of opamp's output resistance, finite unity-gain-frequency, finite open-loop dc gain and slewrate. For this, I have written a veriloga code where I have considered the opamp as thevenin equivalent model i.e. a voltage-controlled-voltage-source (multiplication factor is the small-signal gain with single pole and finite dc gain defined inside the multiplication factor) and output resistance in series with the voltage source. Using this I am correctly recreating the small-signal behavior of the opamp.

Now, the problem is, I need to incorporate the slew-rate (large-signal behavior) also into this. For this, I planned to put the condition like this: once the differential input is greater than a defined (can be controlled from outside) voltage level, output voltage will simply ramp-up with slewrate_plus / ramp-down with slewrate_minus. Is this correct, I mean does this define the slewing correctly? If so, how I can write the code in veriloga (I am new to veriloga and don't know many useful syntaxes). I am stumbling to write the ramping voltage. Please help me.

Regards
Samiran

Title: Re: opamp's slewrate model in verilog-a
Post by Marq Kole on May 12^th, 2010, 7:12am

Hi Samiran,

There is a very useful built-in function to Verilog-A named slew(). You might want to check out the language reference manual for this. It takes two arguments: the expression whose the rate-of-change should be limited and the maximum allowed rate-of-change. It can take an optional third argument if the maximum negative rate-of-change has a different absolute value than the maximum positive rate-of-change. The second argument has to be positive, the optional third argument has to be negative. Sounds like what you need is:

Code:

V(out) <+ slew(gain * V(inp, inn), slewrate_plus, slewrate_minus);

Of course, you probably have more elaborate code to handle the bandwidth and gain requirements, but if you fit in the slew() function slewrate should be taken care of properly.

NB: slew() is an analog operator so generally it cannot appear inside an event, a loop, or a conditional.

Cheers,
Marq

Title: Re: opamp's slewrate model in verilog-a
Post by samiran on May 12^th, 2010, 11:20pm

Hi Marq,

Thanks for the suggestion. My situation is to develop a model of opamp which includes the small-signal and large-signal (specifically slewing for large-step input/high frequency sinusoidal signal) behavior in one model. And also there will be an output buffer stage (mainly to take care of output resistance). But, I am stuck in implementing this as I am not really successfully putting the condition when to start slewing at the output instead of following the small-signal behavior.

In my model, I have a gain stage modeled as VCCS (multiplication factor = g_m, controlling voltage = input voltage), r_o and a cap (C_L) in parallel. This r_o and C_L are setting the dominant pole. And in the output stage its simply a VCVS (multiplication factor = 1, controlling voltage = voltage across the C_L) with a series o/p resistance, R_out.

What I am trying to do to implement slewing, is when input differential voltage is exceeding a certain voltage level, just setting a maximum constant current (I_max) through C_L. But it is not really helping as I am unable to see any slewing for rail-to-rail input step.

Do you have any idea, how this can be implemented?

Thanks for you patience,
with regards
Samiran

Title: Re: opamp's slewrate model in verilog-a
Post by Ken Kundert on May 13^th, 2010, 1:21am

You could use the slew() function, as Marq suggested.

-Ken

Title: Re: opamp's slewrate model in verilog-a
Post by Marq Kole on May 14^th, 2010, 1:58am

The slew() function is defined to operate correctly in both small-signal and large-signal analyses. You can apply this to your capacitance definition:

Code:

I(cap) <+ slew(I(r0), max_rate);
V(cap) <+ idt(I(cap)/Cl, 0);

Marq