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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> Questions about Assura flow of parasitic simulation https://designers-guide.org/forum/YaBB.pl?num=1275362616 Message started by zhangjerome on May 31st, 2010, 8:23pm |
Title: Questions about Assura flow of parasitic simulation Post by zhangjerome on May 31st, 2010, 8:23pm The problem is that I can only save the voltage of top-level and 2nd level nets. When I want to select and save some 3nd or 4th level nets voltage, a warning message says "no valid full path name for net XXX". The LVS is sucessful and shows the layout and schematic matches. I use Cadence Hierarchy editor to do the parasitic simulation. Thank you. |
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