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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> probing external current from subckt enclosed bsource expression https://designers-guide.org/forum/YaBB.pl?num=1275806786 Message started by Kalimero on Jun 5th, 2010, 11:46pm |
Title: probing external current from subckt enclosed bsource expression Post by Kalimero on Jun 5th, 2010, 11:46pm Is it possible to probe a branch current (on the main circuit) from a bsource subckt ?! According to all the available data it should be. subckt bsrc (PLUS MINUS) B (PLUS MINUS) bsource i = exp(v(34,0)) * i("V2:0") ends bsrc ERROR that I get is -> Probe 'I1.V2' does not exist in the netlist V2 is the instance name of a zero volt DC source in my main circuit. I1 is the instance name of my bsource component in the main circuit. I have no problem probing current from other subckts - for example i("I4.V2:0") -> Works just fine .. I4 is an instance name of another subckt on the main circuit. What path name can I use to probe individual devices on the main circuit. ? This problem does not exist for voltage probes. I would be grateful for some insight - |
Title: Re: probing external current from subckt enclosed bsource expression Post by Kalimero on Jun 6th, 2010, 5:41am I did not word that clearly at all .. I guess what I'm asking is how can I probe the current through a component on the main schematic, If i have to do it from inside a subcircuit definition?. using Spectre simulator - Cadence 5.0.0 - icfb.exe version 5.1.0 I am modeling a behavioral current source - the current being a function of a node voltage and an external branch current. I am probing this external current at the plus node of a voltage source on the main circuit ---> V1 (10, 0) vsource DC = 0 However since I am using ADE I am not writing my own netlist so I have to instantiate the bsource as a component and include it in my circuit ... to do this I have to define the device as a subciruit and include the .scs file before running the simulation. B bsource i = v(6,0) * i("V1:0") I reference the voltage probe and the current probe from within the subckt definition as I am not aware of another way to do it. The simulator correctly identifies the voltage I am probing - However it can not locate the instance_name through which i am probing the current, because it looks for it only within the subcircuit containing the bsource expression. As a result I get an error I1.V1 is not found on the netlist -> this is correct because V1 only exist on the main schematic. But it makes no sense to get this error because a signal path is defined from the main circuit file downwards. If I specify a path for a current through a component within another subckt t --> i("I3.V3:0") the probe works fine - However the component I need to probe is on the main circuit - its an analogLib component external to any subcircuits. The work around is to fake a path.to.internal argument for the current probe by packaging a vsource Dc = 0 in a symbol with PLUS MINUS ports and placing an instance of it on the main schematic at the point I need to probe to current - in effect making a bogus subcircuit. Then I can probe the current I need from te main circuit by giving the current probe (in the bsource expression) a path, through the bogus subcircuit instance, to its internal component (vsource dc = 0)... But This is such a clumsy fix .. Yet I am unable to make the current probe work any other way - ... So I was hoping a some feedback on what I may be doing wrong - Thank you .. |
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