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Design >> RF Design >> LNA NF and gdo, zero bias drain conductance understanding help.
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Message started by Thorndike on Jun 9^th, 2010, 12:10pm

Title: LNA NF and gdo, zero bias drain conductance understanding help.
Post by Thorndike on Jun 9^th, 2010, 12:10pm

Hello All,

On reading papers about noise figure in LNA design, I'm coming across the parameter gdo, zero bias drain conductance a lot and having a little difficulty getting my head around this parameter.

I'm thinking that this is the inverse of the channel resistance when Vds=0 and the gate hard switched.

Is that correct? Is there someway that I would be able to simulate this parameter?

Thanks.

Thorn.

Title: Re: LNA NF and gdo, zero bias drain conductance understanding help.
Post by RFICDUDE on Jun 9^th, 2010, 5:17pm

Basically the channel is a voltage controlled conductance (gdo) with a high active output impedance when the device is operation in saturation.

Even in saturation the channel has a conductance which is close to gdo, but the impedance at the drain is much higher because the channel is pinched off. The drain conductance contributes a thermal noise current at the drain terminal, so this is why you see references to gdo with a scaling factor (gamma). The active drain conductance is not equal to gdo because the channel charge density is not constant (somewhat triangular distribution) across the channel. For Vds=0, the charge density is ideally constant across the inverted channel and therefore the channel just looks like a thermal resistance. In saturation (pinchoff) the depletion region raises the impedance at the drain, but the thermal noise current comes straight through. So, you can achieve good gain, but the noise is dominated by the channel thermal noise.

Also, to complicate matters, some of the channel thermal noise leaks into the gate via the gate to channel capacitance. Mostly this is taken to be coupling related to Cgs, but really the coupling is distributed along the channel (quasi static model).

I hope this helps, a little, in regards to why the zero bias drain conductance shows up in CMOS LNA discussions.

Title: Re: LNA NF and gdo, zero bias drain conductance understanding help.
Post by aaron_do on Jun 9^th, 2010, 9:07pm

Hi,

it is the drain-source conductance when V_DS = 0. When V_DS = 0, the device is in the triode region.

I_DS=KW/L((V_GS-V_TH)V_DS-1/2V_DS²)

g_ds = dI_DS/dV_DS = KW/L((V_GS-V_TH)-V_DS)

at V_DS = 0, g_ds = KW/L(V_GS-V_TH)

this is approximately the same as g_m in the saturation region. They are related by the parameter α = g_m/g_d0.

Not sure if that's what you are asking. Why do you say the gate should be hard-switched?

cheers,
Aaron

Title: Re: LNA NF and gdo, zero bias drain conductance understanding help.
Post by Thorndike on Jun 9^th, 2010, 10:39pm

Thanks Aaron and RFICDude.

Makes perfect sense now. I'll revisit the lna papers and see if this adds to my understanding.

On the question of why I was saying it was hardswitched, for some reason the only way I could visualise this was to think of almost a transistor being used as a switch.

Thanks again,

Thorn

Title: Re: LNA NF and gdo, zero bias drain conductance understanding help.
Post by rfcooltools.com on Jun 10^th, 2010, 9:35am

one possibilities I can think of zero bias drain conductance "gdo" is often referred to in the Jfet model.

see http://www.kennethkuhn.com/students/ee351/text/jfet_basics.pdf for example.

Is this paper for a MOSFET or JFET?
thanks
http://rfcooltools.com