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Design >> Analog Design >> current distribution
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Message started by newic on Jun 13^th, 2010, 10:16pm

Title: current distribution
Post by newic on Jun 13^th, 2010, 10:16pm

I have a 20uA Iref as a global current to distribute to local current mirrors. The end point of some circuits need 1m and 2mA current (sub circuit current mirror).

1.)
Is it a common practice to distribute small current. (large current might cause IR drop vs small current might be suspectible to interference)

2.)
Since the multiplication is about 100 times, should I make the sub circuit current mirror x100 bigger? It will be very huge?

comment are welcome :)
although they are simple question ::)

Title: Re: current distribution
Post by raja.cedt on Jun 14^th, 2010, 1:34am

hi,
the main problem with big multiplication number is output current noise, so if you need very clean noise don't do this. If you are not so interested in output current noise then go ahead

One suggestion: if you are doing layout also use 2 fingers and 50 multiplication factor to mitigate LOD effect.

Thanks,
Rajasekhar.

Title: Re: current distribution
Post by carlgrace on Jun 15^th, 2010, 3:14pm

Another thing to watch out for is how long it takes your circuit to recover from power down. If you have a really big multiplication factor, then the output current mirror will be very big, and high capacitance. It may take too long for it to recover from a power-down state.

Have you thought about increasing the reference current to 100uA or so? It is still quite small and shouldn't give you any IR issues.

Carl

Title: Re: current distribution
Post by raja.cedt on Jun 15^th, 2010, 9:47pm

hi,
by the way where you are using this...for example if you are using for any current steering DAC then it's big issue as carlgrace pointed out (mainly for switching)..but there if you can use higher overdrive some how you can escape

Thanks,
Rajasekhar.

Title: Re: current distribution
Post by newic on Jun 15^th, 2010, 10:12pm

Ok. it is reasonable to change to 100uA Iref.

The Iref is generated from Bandgap core circuit which is independent to voltage and temperature. The BG core is only drawn 20uA.

If the core increases to 100uA. it will become sensitive to voltage variation for a given transistor size. It is due to the decrease of gm in the BG loop.

Is it a good idea that to remain the BG core to 20uA and multiply it to 100uA and distribute it as global Iref?

or make BG core and Iref = 100uA?

Title: Re: current distribution
Post by Mayank on Jun 16^th, 2010, 2:45am

Quote:

Is it a good idea that to remain the BG core to 20uA and multiply it to 100uA and distribute it as global Iref?

I dont think so, because all you are doing is multiplying a reference current in two steps instead of one.

Quote:

or make BG core and Iref = 100uA?

Better.

Quote:

If the core increases to 100uA. it will become sensitive to voltage variation for a given transistor size. It is due to the decrease of gm in the BG loop.

Didnt understand this. Pls. explain wot you mean by the above statement. Sensitive to which voltage variation -- Power Supply ??

Title: Re: current distribution
Post by newic on Jun 16^th, 2010, 3:27am

sensitive to power supply variation if BG core current increase.

Title: Re: current distribution
Post by Mayank on Jun 16^th, 2010, 3:45am

Quote:

sensitive to power supply variation if BG core current increase.

I dont think that's gonna be a problem.
Design your opamp loop in such a way that you get desired Power-Supply Rejection at your concerned frequency. (eg, increasing opamp gain)

Since the pmos gm alongwith Opamp Gain A forms a closed loop during BGR operation, I guess increasing GM would make the Power Supply rejection better becuase loop gain is increased.

Another way to look at it is that the Resistive division from vdd to vout, is divided by (1+A*gm*rout).
Higher the gm, lesser the perturbation at output node due to vdd noise.
Wot say ??

--
Mayank

Title: Re: current distribution
Post by subgold on Jun 16^th, 2010, 7:12am

Mayank wrote on Jun 16^th, 2010, 3:45am:

Quote:

sensitive to power supply variation if BG core current increase.

i disagree.

since the bg is generating a reference current, you have to look the power supply sensitivity of the output current, not the voltage.

considering any small-signal variation at the opamp output as an noise source of the PMOS transistor, increasing gm actually enlarge the current noise. if you want to have a high loop gain, it can only be done by by enhancing the opamp gain.

furthermore, even for the voltage PSRR, having larger gm without increasing the transistor size might also not help, because you reduce the voltage headroom, thus get a smaller rout.

in general, i think a mirror ratio of 5 is acceptable, unless you need a very good matching.

Title: Re: current distribution
Post by Mayank on Jun 16^th, 2010, 9:01pm

Quote:

since the bg is generating a reference current, you have to look the power supply sensitivity of the output current, not the voltage.

I think newic was chiefly concerned with BGR voltage PSR, not the current because current PSR is itself very good.

Quote:

considering any small-signal variation at the opamp output as an noise source of the PMOS transistor, increasing gm actually enlarge the current noise. if you want to have a high loop gain, it can only be done by by enhancing the opamp gain.

As far as PSR is concerned, I beg to differ. We want the PSR at opamp output to be very low. We want exactly the same variation at opamp output as it occurs at VDD, so as to keep the VGS of the PMOS same, & hence the same current.

Noise current increases with increasing gm, but that's not what he was talking abt.

Quote:

furthermore, even for the voltage PSRR, having larger gm without increasing the transistor size might also not help, because you reduce the voltage headroom, thus get a smaller rout.

Same explanation as above. Also, larger the transistor size, better the CGS, better the high freq. PSR.

--
Mayank.

Title: Re: current distribution
Post by newic on Jun 19^th, 2010, 9:14pm

Is the PSRR poorer if pmos-nmos current mirror is used instead of opamp.

I used current mirror type to form the gain loop due to simplicity. I think the PSRR is poorer than opamp type.

Title: Re: current distribution
Post by Mayank on Jun 20^th, 2010, 10:56am

Quote:

Is the PSRR poorer if pmos-nmos current mirror is used instead of opamp.

I used current mirror type to form the gain loop due to simplicity. I think the PSRR is poorer than opamp type.

can't say.
In pmos-nmos current mirror, resistance from vdd to output node is increased as it's a cascode config. This will inherently improve PSR.
Opamp Loop is an active loop Rejection.
Do a PSR analysis on your circuit & find out.

Title: Re: current distribution
Post by tzg6sa on Jun 21^st, 2010, 1:07am

raja.cedt wrote on Jun 14^th, 2010, 1:34am:

hi,
the main problem with big multiplication number is output current noise, so if you need very clean noise don't do this.

Please correct me if I am wrong, but with higher multiplication ratio the SNR will be better, because the noise power is proportional to the transconductance of the output device, while the signal power is proportional to the square of the transconductance. (assumed that the current noise is of interest)

Title: Re: current distribution
Post by Mayank on Jun 21^st, 2010, 1:18am

Quote:

By signal , i assume you mean the small signal input (ac input ) to the block.

small signal power is dependent on Transconductance of Input Devices, not the current mirrors. [because current mirrors/sources/sinks do not lie in signal path]
WHILE
noise current injection we are talking about here is dependent on square root of Transconductance of Current Mirrors.

Hence, Input device gm should be large, not the current mirrors.

Hence, Raja stands correct.