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Design >> RF Design >> Fractional PLL fundamentals
https://designers-guide.org/forum/YaBB.pl?num=1276576001

Message started by Mayank on Jun 14^th, 2010, 9:26pm

Title: Fractional PLL fundamentals
Post by Mayank on Jun 14^th, 2010, 9:26pm

Suppose, i have a Fractional PLL with Δ-Σ modulation on division bits.

Does this type of a Fractional PLL ever achieve a periodic-steady state of operation ??

Meaning --

Theoretically speaking, if Loop Filter BW is much lesser (say a decade lesser) than Δ-Σ modulation Frequency, then Loop Filter should filter out all high-frequency components & we should get a constant desired frequency (say, 800.88 MHz)
OR
Maybe, does the PLL operating frequency keeps shifting with changing division bits from the Δ-Σ modulator ?? (say, b/w 800, 801 depending on modulation depth)

If someone can clarify.

Title: Re: Fractional PLL fundamentals
Post by rfcooltools.com on Jun 14^th, 2010, 10:49pm

The PLL has an analog voltage to frequency converter at the business end of PLL and excluding phase noise the output frequency will be exact if the filtering before this voltage is sufficient enough then the frequency will closely approximate a steady state.

It will only approximate a steady state condition where the approximation depends on fractional offset/loop bandwidth/KV/Cpcurrent and comparison frequency. As you state if the loop bandwidth is reduced by several orders then the voltage on the varactor will be relatively constant thus the oscillation frequency closer to target. but the jumping around between two frequencies will only be evident if the fractional frequency is close to the loop filter cutoff.

for a VCO the time varying signal on the varactor will have the following equation
Vout(t)=A*sin(wt+kv*integ(x(t)))
x(t) being the voltage on the varactor. If x(t) becomes small as is the case when the loop bandwidth is minimal then the VCO aproximates a sine wave carrier with AM or as you put ithopping between to frequencies (only integral restricted) .
Vout(t)=A*sin(wt+kv*integ(x(t))) ~=A*(1+kv*integ(x(t))*sin(wt))

http://rfcooltools.com

Title: Re: Fractional PLL fundamentals
Post by Mayank on Jun 14^th, 2010, 11:06pm

Quote:

Theoretically speaking, if Loop Filter BW is much lesser (say a decade lesser) than Δ-Σ modulation Frequency, then Loop Filter should filter out all high-frequency components & we should get a constant desired frequency (say, 800.88 MHz)

@ Others : Do we all agree with this statement ??

@ rfcooltools : That being said & considered true to our knowledge, Can we run PSS/pnoise analysis on Fractional PLLs then ??

Actually, this question kinda sprouted from my recent query @ mixed-signal forum --
http://www.designers-guide.org/Forum/YaBB.pl?num=1276575200/0#0

Title: Re: Fractional PLL fundamentals
Post by pancho_hideboo on Jun 15^th, 2010, 5:32am

Mayank wrote on Jun 14^th, 2010, 11:06pm:

Quote:

@ Others : Do we all agree with this statement ??

Strictly speaking, No. But it is very enough constant frequency.

Mayank wrote on Jun 14^th, 2010, 11:06pm:

@ rfcooltools : That being said & considered true to our knowledge, Can we run PSS/pnoise analysis on Fractional PLLs then ??

No, although I don't know what simulator you use as "PSS/Pnoise".
See http://www.designers-guide.org/Forum/YaBB.pl?num=1268969030

The followings are general notes for you.

- Always describe correct tool's name and vendor's name which you use as tool or simulator.
- Don't do multiple posts which are same content.
- Don't request source code or behavioral model without any efforts.
- There are many simulators which have analyses called as PSS, PAC and Pnoise.
- Describe in detail with using correct terminologies.
- Warnigns are different from Errors.
- ADS is not name of simulator.
- There is no tool which name is Cadence.
- Don't use Direct Plot of Cadence ADE blindly without knowing definition.
- All gains in Direct Plot of Cadence ADE are "right", "true" and "practical" voltage gain.
- Don't mix up Simulation with Post Processing. They are completely different phase.
- MATLAB are different from Simulink.
- Learn measurements using actual instruments. Not "EDA Tool Play

Title: Re: Fractional PLL fundamentals
Post by rfcooltools.com on Jun 15^th, 2010, 10:41am

Mayank,
PSS (spectre) would have to run at least for a time where the period fref and the period vco are coincident (which is by the way the fractional offset), which may converge if the iterratio is loose enough, but the catch 22 is with loose iterratio the resulting pnoise simulation will have incorrect values at close in offsets. So the answer is I doubt you will get the result you want and if you do it will have so many warnings at each offset that you won't be confident.

http://rfcooltools.com

Title: Re: Fractional PLL fundamentals
Post by Ken Kundert on Jun 15^th, 2010, 5:52pm

The sequence generated by the fractional-N modulator is pseudo-random, meaning that it eventually repeats. Thus, the fractional-N synthesizer does eventually generate a periodic signal, though the period is the length of the pseudo-random sequence, which is very long relative to the duration of one cycle of the output signal.

You do not say why you are interested in knowing whether the output of the fractional-N synthesizer is periodic. If is because you want to run a PSS analysis, then you posted your question to the wrong board. That would be an RF simulation question, and not an RF design question. If that is your question, then the answer is in effect no, because the period is so long relative to the duration of one cycle of the output signal as to make it completely impractical to run PSS with that period.

-Ken

Title: Re: Fractional PLL fundamentals
Post by sheldon on Jun 15^th, 2010, 7:15pm

Mayank,

For what is worth,

The input frequency of the PLL is harmonically related to the output
frequency of the PLL. However, this does not mean that a fractional-N
PLL has a periodic steady-state. One of the reasons for selecting the
Fractional-N PLL architecture is that it does not have a periodic
steady-state. The non-periodic nature of the Fractional-N PLL
contributes to lower spurious response.

Best Regards,

Sheldon

Title: Re: Fractional PLL fundamentals
Post by Mayank on Jun 15^th, 2010, 9:17pm

@ rfcooltools & Ken : That explains the reason why people dont do PSS on Fractional PLLs.

@ Ken : Integer PLL has a periodic Steady state of Operation. I wanted to know if the LPF of Fractional PLL filters modulation Noise & provides a clean enough fractional frequency at PLL output. Sorry Boss, made it sound like a simulator query, but that pss question came to my mind just because noOne here runs pss on Fractional PLL. Thought would ask why alongwith.

@ Sheldon : SDM will eventually repeat it's pseudo-random sequence as Ken says, but since that Time Period is much longer than the Time Period of the PLL Operating Frequency, the spurs would be suppressed.

@ everyone : So,
1. is the Fractional PLL's frequency clean & stable enough for Analog Sampling of a Signal ?
2. To check the effect of Fractional PLL clock's effect on Sampling, if i use an ideal sampler operating at PLL clock, What would be the major spurs i would be observing in SNDR plot of Sampled Signal ??

--
Mayank.