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Design >> Mixed-Signal Design >> Cap size for pipelined ADC (matching question)
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Message started by carlgrace on Jun 15^th, 2010, 9:47am

Title: Cap size for pipelined ADC (matching question)
Post by carlgrace on Jun 15^th, 2010, 9:47am

I'm a bit confused about choosing caps based on mismatch data. Say, for instance, that the process I'm using claims I need 1.2 pF of capacitance for a three-sigma mismatch of 0.1% (I'm trying to build a 10-bit ADC). Now, does that mean both the sampling and feedback cap need to be 1.2 pF to get this matching, or is the total capacitance I'm sampling with (two caps) need to be 1.2 pF so each cap can be 600 fF? The design manual is not clear about this.

Carl

Title: Re: Cap size for pipelined ADC (matching question)
Post by RobG on Jun 16^th, 2010, 5:27pm

Who knows... Generally the number is between two caps of equal size, so you would need both caps to be 1.2pF. However, I'd check with the guys who gave you the number!

Title: Re: Cap size for pipelined ADC (matching question)
Post by Mayank on Jun 16^th, 2010, 9:57pm

Both need to be 1.2pF individually. That's how i would interpret it.

--M

Title: Re: Cap size for pipelined ADC (matching question)
Post by Maks on Jun 18^th, 2010, 7:23am

carlgrace wrote on Jun 15^th, 2010, 9:47am:

And don't forget about the mismatch induced by the layout and capacitive coupling to the nets surrounding the unit caps.

Title: Re: Cap size for pipelined ADC (matching question)
Post by vivkr on Jun 22^nd, 2010, 1:56am

Read the process manual carefully. Usually, they specify how the mismatch is defined and sometimes even the test structure used. Note that the definition may not be consistent with the setup used.

Nonetheless, it says somewhere whether the variation is computed for mismatch between 2 identical caps of size C or if it would be the variation of 1 cap with respect to its mean value.

Vivek

Title: Re: Cap size for pipelined ADC (matching question)
Post by loose-electron on Jun 27^th, 2010, 10:42am

Don't forget the KT/C calculation as well. 10 bits?
I would get 3-6dB noise margin on just that.

That might dictate a larger set of capacitors, you need to
go do the math and put margin into the design.

Title: Re: Cap size for pipelined ADC (matching question)
Post by carlgrace on Jun 27^th, 2010, 3:31pm

I did do the kT/C noise calculation and I'm mismatch limited at 10 bits for my signal swing. Getting answers out of TSMC is like getting blood out of a stone. I'm sure they have a document with detailed mismatch data. Why they won't send it to me and seem to be deliberately misunderstanding my questions is beyond me. I'm going to do a couple simple simulations with the statistical models and see if they correlate with what I expect. Thanks for the help, everyone!

Carl