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Simulators >> AMS Simulators >> Interface elements problem in spectreverilog
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Message started by Murat H. Eskiyerli on Jun 16th, 2010, 3:58am

Title: Interface elements problem in spectreverilog
Post by Murat H. Eskiyerli on Jun 16th, 2010, 3:58am

I am just trying to debug Cadence setup for mixed mode simulation. I am just trying to use spectreverilog for simple AMS simulations (A/d).  I created a very simple schematic with a single inverter described in verilog and a voltage pulse source driving it. When I check how the design is partitioned, it seems to be correct with voltage source identified as analog, the inverter as digital and the net between them as mixed-signal. I also copied MOS interface elements from analogLib and updated CDF properties. The problem starts when I try to netlist and simulate the circuit. I keep getting the following error message and the simulation fails.

Any ideas on what could be going on?

Regards

\o *USRWARN: You have used nondetailed Interface Element (IE) Generation
\o which will have less IE modeling accuracy than detailed IE Generation.
\o You should make sure that:
\o      1. All digital instance terminals connected at the same
\o Interface Net will have compatible logic and voltage thresholds.
\o      2. The loading and driving capabilities of all digital terminals
\o connected at the same Interface Net can be modeled with one IE
\o without significant loss of accuracy.
\o *USRERR:  Net in, in module test_artisan2, lib ROIC, view schematic
\o      requires the generation of Hierarchical Interface Element (IE) inside
\o      a cellview having the view name that is a member of the analog
\o      or digital stop view set. Such an IE will be ignored by the simulator.
\o      Please change your design to avoid this limitation.
\o  Unable to generate hierarchical interface elements for Network design (cell: test_artisan2, lib: ROIC, view: config)
\o Netlist Error: IE Generation-- Must correct Interface Element Generation errors before continuing with netlisting.
\o       ...unsuccessful.

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