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Design >> RF Design >> CML Ringoscillator
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Message started by znieH on Jun 17^th, 2010, 2:57am

Title: CML Ringoscillator
Post by znieH on Jun 17^th, 2010, 2:57am

Hi,

my first project in Circuit Designing is a CML Ringoscillator, that consists of 53 Inverter. The Inverters are designed as differential pair of SiGe HBTs. I perform PreLayout as well as PostLayout (transmission lines included) simulations in Spectre.

:o What is strange for me, is that the output frequency of the PostLayout simulation with parasitics is faster (about 20%). I think that is because there is an additional inductance in series to the collector resistance (Rc) through adding the transmission lines, but I can not really explain for myself why. Can anybody help me?

Regards and thanks in advance.

Title: Re: CML Ringoscillator
Post by rfcooltools.com on Jun 17^th, 2010, 4:35pm

Time const is set by R || Ccb and in parallel with (Cbe+Ce of the next device ). So it may be that the impedance at the emitter has increased possibly because of resistance to the current source.

http://rfcooltools.com

Title: Re: CML Ringoscillator
Post by Mayank on Jun 17^th, 2010, 9:10pm

Please Check your models.
20% faster is a huge difference in simulation b/w layout & schematic simulation.
Generally, post-layout is slower due to added routing capacitances.
I dont think interconnect inductance would be huge enough to cause a visible effect.

Quote:

Time const is set by R || Ccb and in parallel with (Cbe+Ce of the next device ). So it may be that the impedance at the emitter has increased possibly because of resistance to the current source.

An increase in Impedance would increase the Time Constant, thereby decreasing frequency.

Title: Re: CML Ringoscillator
Post by rfcooltools.com on Jun 17^th, 2010, 10:31pm

Mayank,

What do you think the time const will increase or decrease?

http://rfcooltools.com

Title: Re: CML Ringoscillator
Post by Mayank on Jun 17^th, 2010, 11:27pm

Below is the attached figure as i understand....

Title: Re: CML Ringoscillator
Post by znieH on Jun 18^th, 2010, 12:41am

First of all thanks for your andwers.

@Mayank
Please Check your models. 20% faster is a huge difference in simulation b/w layout & schematic simulation. Generally, post-layout is slower due to added routing capacitances.

It is a new process, designers told me automatic post layout simulation is not yet possible. Parasitics have to be included by hand, so there is at the moment only the model of the transmission lines in series with its resistance, no routing capacitances included.

I dont think interconnect inductance would be huge enough to cause a visible effect.
I added in the Pre-Layout a inductance in series to Rc and the output frequency increase as in the Post-Layout simulation. Designers told me its a shock inductance but I asked google and found nothing that explain my problem. (Only for understanding the designers are french and their english is not so good, so I have to find out by myself.)

Title: Re: CML Ringoscillator
Post by znieH on Jun 18^th, 2010, 12:47am

Could it be that the matching between the inverter stages is improved by the inductor in series to Rc??

Hope I didn't say something stupid ::)

Title: Re: CML Ringoscillator
Post by Mayank on Jun 18^th, 2010, 3:16am

Quote:

It is a new process, designers told me automatic post layout simulation is not yet possible. Parasitics have to be included by hand, so there is at the moment only the model of the transmission lines in series with its resistance, no routing capacitances included.

Which transmission lines are you talking about ?
Are you including any such T-line models in your schematic ??

Quote:

I added in the Pre-Layout a inductance in series to Rc and the output frequency increase as in the Post-Layout simulation. Designers told me its a shock inductance but I asked google and found nothing that explain my problem. (Only for understanding the designers are french and their english is not so good, so I have to find out by myself.)

Havent heard of any shock inductance arising at source node, unless you deliberately place one.

Title: Re: CML Ringoscillator
Post by znieH on Jun 18^th, 2010, 3:53am

Are you including any such T-line models in your schematic ??

Yes, it is only the vias that had to be calculated by hand.

Havent heard of any shock inductance arising at source node, unless you deliberately place one.

I think I found what they have meant. The effect is called SHUNT PEAKING. And sorry if I was not precise enough, but I was talking of HBTs and the inductance is between the node of the collector and the Rc resistance.

Title: Re: CML Ringoscillator
Post by rfcooltools.com on Jun 18^th, 2010, 9:31am

Mayank,

TC=2*pi/(RC)
You have it inverted in your diagram.

Title: Re: CML Ringoscillator
Post by Mayank on Jun 20^th, 2010, 10:47am

Last Time i checked, Time Constant is RC or L/R.

F-3db = 1/(2*pi*TC) though if that's what you are referring to.