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Modeling >> Behavioral Models >> Modeling of Arbitrary Phase Shift in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1277271688

Message started by samiran on Jun 22^nd, 2010, 10:41pm

Title: Modeling of Arbitrary Phase Shift in Verilog-A
Post by samiran on Jun 22^nd, 2010, 10:41pm

Dear All,

I want to write a verilog-A code which provides an arbitrary phase shift (which can be controlled as a parameter) of the actual o/p signal.

Is there any in-built function already available to do so? If not, how can I achieve this?

Regards
Sam.

Title: Re: Modeling of Arbitrary Phase Shift in Verilog-A
Post by pancho_hideboo on Jun 24^th, 2010, 7:26am

samiran wrote on Jun 22^nd, 2010, 10:41pm:

Is there any in-built function already available to do so?

No.

samiran wrote on Jun 22^nd, 2010, 10:41pm:

If not, how can I achieve this?

Synthesize aribitrary phase shifter using cascaded connected All-pass Filters.

http://en.wikipedia.org/wiki/All-pass_filter

Also see http://www.designers-guide.org/Forum/YaBB.pl?num=1233062253/1#1

Title: Re: Modeling of Arbitrary Phase Shift in Verilog-A
Post by Ken Kundert on Jun 24^th, 2010, 11:28am

You could use the absdelay() function. Unfortunately, Cadence's implementation does not work in the small-signal analyses. It has been that way for 14 years, so I guess they are not going to fix it.

It might help if you explained what you are trying to do. Verilog-A is a hardware description language, so it might help you to think about how you would implement this in hardware.

-Ken

Title: Re: Modeling of Arbitrary Phase Shift in Verilog-A
Post by pancho_hideboo on Jun 24^th, 2010, 11:38am

Ken Kundert wrote on Jun 24^th, 2010, 11:28am:

You could use the absdelay() function.

I don't think absdelay() can be used as phase shifter.

Transfer function of absdelay() is exp(-j*ω*T_delay).
So you can get only phase shift which changes linearly with frequency.