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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> adc verilogA errors! https://designers-guide.org/forum/YaBB.pl?num=1277453893 Message started by casual on Jun 25th, 2010, 1:18am |
Title: adc verilogA errors! Post by casual on Jun 25th, 2010, 1:18am The code was copied from designers-guide.org. So it should be correct. I got several errors about the code and i do not know how to solve it. I am using IC5141, mmsim61. The errors i got: Line 36 "for(i = bits-1; i >= 0; i = i-1 )<<--? begin" Line 36 Error: In for-loop control, genvar expression can only consists of integer constant or other unrolled genvar variables expression. Line38 "result[i]<<--? = vdd;" Error: Genvar variable `i' is referenced within incorrect for-loop. Line41 "result[i]<<--? = 0.0;" .... many more Sound like those errors occurs whenever i use [i] or i Is it my verilogA compiler too old? I am not sure how to check the version. Code:
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Title: Re: adc verilogA errors! Post by Marq Kole on Jun 25th, 2010, 7:17am I would suggest using a later version of Cadence MMSIM, version 7.2 or later preferably. Lately Cadence have made some changes in the supported syntax for analog for loops and the use of genvars. Actually the restrictions they apply to array indexes are completely unnecessary and not supported by anything in the standard. Cheers, Marq |
Title: Re: adc verilogA errors! Post by casual on Jun 25th, 2010, 8:35am do you have any workaround or methods other than using mmsim72?? :'( |
Title: Re: adc verilogA errors! Post by pancho_hideboo on Jun 25th, 2010, 9:04am supermoment wrote on Jun 25th, 2010, 8:35am:
Try to modify like following, although I don't know vendor's name of which you use simulator. Quote:
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Title: Re: adc verilogA errors! Post by casual on Jun 25th, 2010, 11:25pm sorry, i i posted the old version one. The new version had fixed the "Bits" problem before the 1st post. Code:
I got the same error message as in the first post. It is related to the loop with "i" I am using Cadence mmsim61. |
Title: Re: adc verilogA errors! Post by casual on Jun 26th, 2010, 12:40am I have tried the method, but it does not work as well line 6: "'<<- -? define Bits 8" line 26: "output [0:'Bits<<--? -1] out;" I am new in VerilogA. Sounds like I could not use 'define Bits 8 I also tried the to use generate i; in both cases ( with 'define Bits 8 or parameter interger Bits = 8 from [1:24];) But it does not work at all... :D |
Title: Re: adc verilogA errors! Post by casual on Jun 26th, 2010, 1:01am Thanks a lot. it works eventually.. The mistake i made was using ' instead of ` I learned the lesson. :) |
Title: Re: adc verilogA errors! Post by pancho_hideboo on Jun 26th, 2010, 1:16am supermoment wrote on Jun 26th, 2010, 1:01am:
http://www.designers-guide.org/Forum/YaBB.pl?num=1264401024/1#1 All threads after following are unnecessary. http://www.designers-guide.org/Forum/YaBB.pl?num=1277453893/3#3 |
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