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Message started by jimiblues on Jun 27th, 2010, 11:39am

Title: substrate loss in CPW transission lines (in CMOS)
Post by jimiblues on Jun 27th, 2010, 11:39am
In a lot of transmission line literatures, it is mentioned that since the CMOS substrate is conductive, the image current induced in the substrate will introduce loss to the transmission line.

I can imagine that the induced image current will decrease the unit inductance value of the line, but I don't understand why the image current will make the line more lossy.
Can some one explain this to me?

Thank you very much

Jimiblues

Title: Re: substrate loss in CPW transission lines (in CMOS)
Post by RFICDUDE on Jun 28th, 2010, 3:11am
The line loss increases because the eddy currents, induced by signal current on the line, dissipate into the conductive substrate. If the substrate were a perfect conductor then only the inductance of the line would be affected.

Essentially the line is magnetically coupled to the conductive substrate resulting in the eddy currents.

One interesting point is that the substrate needs to be conductive enough for the eddy currents to be appreciable before the losses due to eddy currents is noticeable. For conductivities lower than that needed for eddy currents to be significant, the loss in the substrate matters more for the capacitive coupling from the line to the lossy substrate.

I am not aware of a good reference that clearly delineates the transition from losses due to capacitive coupling to substrate versus eddy current induced into the substrate. It would be nice to see the transition as a function of the conductivity of the substrate and perhaps the line dimensions.

Title: Re: substrate loss in CPW transission lines (in CMOS)
Post by rfcooltools.com on Jun 28th, 2010, 11:43am
The eddy currents will facilitate the dissipation of power into a real load (substate resistance) and thus loss of signal occurs.  

http://rfcooltools.com

Title: Re: substrate loss in CPW transission lines (in CMOS)
Post by jimiblues on Jun 30th, 2010, 10:14am

RFICDUDE wrote on Jun 28th, 2010, 3:11am:
The line loss increases because the eddy currents, induced by signal current on the line, dissipate into the conductive substrate. If the substrate were a perfect conductor then only the inductance of the line would be affected.

Essentially the line is magnetically coupled to the conductive substrate resulting in the eddy currents.

One interesting point is that the substrate needs to be conductive enough for the eddy currents to be appreciable before the losses due to eddy currents is noticeable. For conductivities lower than that needed for eddy currents to be significant, the loss in the substrate matters more for the capacitive coupling from the line to the lossy substrate.

I am not aware of a good reference that clearly delineates the transition from losses due to capacitive coupling to substrate versus eddy current induced into the substrate. It would be nice to see the transition as a function of the conductivity of the substrate and perhaps the line dimensions.



Hi rfdude,

Thanks or the reply.

I understand this now. the loss come from the magneticly induced current flowing in the lossy conducting substrate. If the substrate is totally insulating, or perfectly conducting, this loss is gone. although the perfect conducting substrate will greatly decrease the inductance of the line.

i also found a website on this.
http://bmf.ece.queensu.ca/mediawiki/index.php/Transmission_Line_Design_on_Silicon
it has a equation on this resistance, Rl. I doubt on this equation, and i calculated the value of this resistance at 10GHz, (and subsrate conductivity as 10S/m, line width of 10um), it is almost 20Mohm/m. It is so big comparing to the impedance of the inductance, which means the loss due to the substrate is omitable. I couldn't understand this.

Do you have some comments on this?

Cheers,
Jimiblues

Title: Re: substrate loss in CPW transission lines (in CMOS)
Post by jimiblues on Jun 30th, 2010, 10:15am

rfcooltools.com wrote on Jun 28th, 2010, 11:43am:
The eddy currents will facilitate the dissipation of power into a real load (substate resistance) and thus loss of signal occurs.  

http://rfcooltools.com



Hi rfcootools,
Thanks you for the explaination

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