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Message started by mustansirmukadam on Jun 29th, 2010, 9:33am

Title: Monte Carlo analysis for resistors in TSMC 65nm
Post by mustansirmukadam on Jun 29th, 2010, 9:33am

Hi

I am trying to do statistical simulations for RF resistors in the TSMC 65nm process. However, I am not able to figure out what model files to include so that monte carlo simulations in Cadence are able to use statistical data instead of the nominal corner.

For transistors I do the following:
If I am using nch_lvt (low vt NFET) i do the following in the model library:
1. Uncheck tt_lvt
2. Check mc_lvt
3. Check stat
4. Check stat_mis_lvt

I did something similar for rppoly resistors but the statistical data shows no spread in results which indicates it's just taking data from the nominal corner.

Could someone help?

Title: Re: Monte Carlo analysis for resistors in TSMC 65nm
Post by Mayank on Jun 30th, 2010, 3:34am

Genearlly, there's a switch which should be enabled for MC analyses.

Pls. check in stat & mc files if this switch has been enabled.
Also, pls. check if you have setup your MC analysis correctly.


Title: Re: Monte Carlo analysis for resistors in TSMC 65nm
Post by Geoffrey_Coram on Jul 1st, 2010, 5:46am

If you're getting mismatch for the lvt transistors, then you can probably skip Mayank's suggestions.

Are you sure that the model library has statistics for the resistors?

Title: Re: Monte Carlo analysis for resistors in TSMC 65nm
Post by mustansirmukadam on Jul 15th, 2010, 8:50am

I do get mismatch for my lvt transistors. It's just the resistors that don't seem to have any mismatch switch per say. According to the model library there is some statistical information for resistors but I can't be too sure. Do you have any experience with the TSMC 65nm design kit?

Title: Re: Monte Carlo analysis for resistors in TSMC 65nm
Post by mustansirmukadam on Jul 15th, 2010, 8:54am

At this point I'm not even able to do corner simulations for resistors. Even that would help.

Title: Re: Monte Carlo analysis for resistors in TSMC 65nm
Post by Geoffrey_Coram on Jul 19th, 2010, 5:37am

Which variant - LP, G, GP?

What does your .lib statement look like in the netlist?  I looked at one 65nm model library file, and it looked like each component had to have its own .lib statement -- .lib TT got MOS, but you also would need to have .lib TT_RES in your netlist to be able to simulate any resistors.

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