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Design Languages >> Verilog-AMS >> Problem with slew() function in Verilog-A
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Message started by carlgrace on Jun 29th, 2010, 10:44am

Title: Problem with slew() function in Verilog-A
Post by carlgrace on Jun 29th, 2010, 10:44am

I'm trying to add slew-rate limiting to an op-amp model in Verilog-A.  I have the linear settling doing what I expect using the laplace_nd() function and everything works fine up to that point.

However, when I try to wrap the slew function around it I get crazy results.  For example, the statement:

Aout = laplace_nd(Vout_temp, {gdc}, {1 , tau});  

does exactly what it should.  But, if I want to model limited current with:

Aout = slew( laplace_nd(Vout_temp, {gdc}, {1 , tau}),slewrate);

then I get outputs in hundreds of volts of kilovolts!  I set the slewrate at 1e9, or 1V/ns.  I also tried a lot of other slewrates in case I didn't understand the definition but it doesn't work!  Can someone please give me a hint on how this slew() function works?

Thanks,
Carl

Title: Re: Problem with slew() function in Verilog-A
Post by Geoffrey_Coram on Jun 29th, 2010, 12:39pm

Have you tried slewing a simpler expression?  Try a basic sine wave, or maybe
V(out) <+ slew(V(in), slewrate)
and then give it a pulse source where you know the rise time.

Title: Re: Problem with slew() function in Verilog-A
Post by Marq Kole on Jul 5th, 2010, 4:22am

It is always a good idea when developing a model to assign the results of a analog operator to a separate variable. Both slew and laplace_nd are analog operators.


Code:
Aout_filt = laplace_nd(Vout_temp, {gdc}, {1 , tau});
Aout = slew(Aout_filt, slewrate);


Try to work from information on what goes in and out of the function. If everything works fine, you can start to optimize your code by folding expressions together. Actually, that isn't really an optimization as it will have no influence on the generated code and make your model less readable. Let the compiler do the optimizations - that's what it's supposed to do!

Cheers,
Marq

Title: Re: Problem with slew() function in Verilog-A
Post by carlgrace on Jul 6th, 2010, 1:04pm

As an update, I installed the latest version of Mentor ADMS and the problem went away.  I think either slew or laplace_nd was entirely implemented on the version (several years old I should think) that I was using.  All it took was two days of rage before I made sure I was using the most updated tool.

And Marq, thank you for the advice!  I have update my code for readability.

Carl

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