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Design Languages >> Verilog-AMS >> Module instantiation using Generate in Verilog-A
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Message started by kumar on Jul 2^nd, 2010, 1:50am

Title: Module instantiation using Generate in Verilog-A
Post by kumar on Jul 2^nd, 2010, 1:50am

Hi all,

I am using a generate statement to instantiate a delay module (cur_starved_delay) 11 times. The basic idea is to model a 11 stage ring oscillator using current starved delay cell. But i get syntax error in generate statement. Can anyone help me with this. The code is attached below.

`include "constants.vams"
`include "disciplines.vams"

module cur_starved_delay (Vin,Vbias_p,Vbias_n,Vdd,Vss, Vout);

parameter real C_load = 1e-12;
parameter real Kp = 1;
parameter real Kn = 1;
parameter real Vt = 0.2;
parameter real pos_tol = 0.2;
parameter real neg_tol = -0.2;

input Vin,Vbias_p,Vbias_n,Vdd,Vss;
output Vout;

voltage Vin,Vbias_p,Vbias_n,Vdd,Vss,Vout;

voltage V_swing,Vsg_p,Vgs_n;
current I_p,I_n;
real Td_p,Td_n,V_ph;

analog begin

V(V_swing) <+ V(Vdd) - V(Vss);
V(Vsg_p) <+ V(Vdd) - V(Vbias_p);
V(Vgs_n) <+ V(Vbias_n) - V(Vss);
I(I_p) <+ Kp*pow((V(Vsg_p) - Vt),2);
I(I_n) <+ Kn*pow((V(Vgs_n) - Vt),2);

if ((V(Vin) <= V(Vss) + pos_tol) && (V(Vin) >= V(Vss) - neg_tol)) begin
Td_p = (V(V_swing)/I(I_p))*C_load;
end
else if ((V(Vin) <= V(Vdd) + pos_tol) && (V(Vin) >= V(Vdd) + neg_tol))
Td_n = (V(V_swing)/I(I_p))*C_load;

@(cross(V(Vin)-(V(V_swing)/2),+1)) begin
V_ph = V(Vss);
end
@(cross(V(Vin)-(V(V_swing)/2),-1)) begin
V_ph = V(Vdd);
end
V(Vout) <+ transition(V_ph,0,Td_p,Td_n);
end

endmodule

module multiphase_vco(Vbias_p,Vbias_n,Vdd,Vss, out);

parameter integer ZERO_BIT = 0;
parameter integer NO_STAGE = 11 from [3:67];
parameter real C_load = 1e-12;
parameter real Kp = 1;
parameter real Kn = 1;
parameter real Vt = 0.2;
parameter real pos_tol = 0.2;
parameter real neg_tol = -0.2;

genvar i;

input Vbias_p,Vbias_n,Vdd,Vss;
output [NO_STAGE-1:0] out;

voltage Vbias_p,Vbias_n,Vdd,Vss;
electrical [NO_STAGE-1:0] out;
electrical [NO_STAGE:0]ph_out;

generate
for (i =1;i<=11;i=i+1) begin
cur_starved_delay #(.C_load(C_load),.Kp(Kp),.Kn(Kn),.Vt(Vt),.pos_tol(pos_tol),.neg_tol(neg_tol))
D_i(.Vin(ph_out[i-1]),.Vbias_p(Vbias_p),.Vbias_n(Vbias_n),.Vdd(Vdd),.Vss(Vss),.Vout(ph_out[i]));
end
endgenerate

analog begin
V(ph_out[0]) <+ V(ph_out[NO_STAGE]);

@(initial_step) begin
V(ph_out[ZERO_BIT]) <+ V(Vss);
end

end

endmodule

Title: Re: Module instantiation using Generate in Verilog-A
Post by kumar on Jul 2^nd, 2010, 5:59am

I referred to Verilog-AMS ref Manual Ver. 2.3.1(Pg 139). I even tried comenting generate and endgenerate statements but still it gave me error in for loop. In Verilog-A ref manual there is no detail for module instantiation using generate. They have given few examples only for some expression statements but not module instantiation

Title: Re: Module instantiation using Generate in Verilog-A
Post by pancho_hideboo on Jul 2^nd, 2010, 6:07am

kumar.g wrote on Jul 2^nd, 2010, 1:50am:

genvar i;

generate
for (i =1;i<=11;i=i+1) begin
cur_starved_delay #(.C_load(C_load),.Kp(Kp),.Kn(Kn),.Vt(Vt),.pos_tol(pos_tol),.neg_tol(neg_tol))
D_i(.Vin(ph_out[i-1]),.Vbias_p(Vbias_p),.Vbias_n(Vbias_n),.Vdd(Vdd),.Vss(Vss),.Vout(ph_out[i]));
end
endgenerate

What is "D_i" ?

Try to write "D[i]" or "D<i>", although I don't confirm them.

Title: Re: Module instantiation using Generate in Verilog-A
Post by kumar on Jul 2^nd, 2010, 8:17am

D_i is just component name. It doesn't get changed. The simulator will assign D_i.Inst[i] as each components name. So I guess we can't change D[i] or D<i>.

Title: Re: Module instantiation using Generate in Verilog-A
Post by Marq Kole on Jul 5^th, 2010, 2:37am

There is nothing wrong with the name D_i. You cannot even use D[i] or D<i> according to the standard - the array reference is provided in the scope of the generate block.

Are you certain that the loop generate statements are supported by your simulator? To my knowledge - which may be outdated - no commercial Verilog-A compiler currently supports the generate constructs.

Cheers,
Marq

Title: Re: Module instantiation using Generate in Verilog-A
Post by kumar on Jul 5^th, 2010, 6:38am

I am not sure with that. But I use Cadence ICFB 5.14

Title: Re: Module instantiation using Generate in Verilog-A
Post by Marq Kole on Jul 5^th, 2010, 7:53am

With that version of Cadence IC - assuming you use the spectre versino that is part of that release - you will not get any support for features newer than Verilog-AMS 2.1 annex C. Although I would first suggest to start using Cadence MMSIM, you will also not see any support for the generate statements in the latest versions of Spectre. However Cadence MMSIM (which includes Spectre) will have the rest of the Verilog-A support more up to date and generally faster.

I'm afriad you will have to rework your model without the generate statement.

Cheers,
Marq

Title: Re: Module instantiation using Generate in Verilog-A
Post by kumar on Jul 6^th, 2010, 12:14am

Thank you very much for the clarification