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Design Languages >> Verilog-AMS >> port probes: VerilogAMS vs VerilogA
https://designers-guide.org/forum/YaBB.pl?num=1278417828

Message started by Misha on Jul 6^th, 2010, 5:03am

Title: port probes: VerilogAMS vs VerilogA
Post by Misha on Jul 6^th, 2010, 5:03am

Hello,
I have a VerilogA model that is working well in Spectre/APS. How I'm trying to simulate the design with Cadence AMS and get an error during the elaboration stage:

Quote:

B = I(<mp>)/area;
|
ncelab: *E,SYERROR (...<mypath>/veriloga/verilog.vams,102|10): Port probes are not supported in modules with hierarchy.

This a cell with some RLC components instantiated and in the code I'm trying to sens the current through one terminal. In the verilogA code this line uses the following syntax:
B = I(mp,mp) / area;

I tried naming this branch explicitly, but it does not help.
Any idea how I can work around this?

Thanks a lot in advance!

Misha

Title: Re: port probes: VerilogAMS vs VerilogA
Post by Geoffrey_Coram on Jul 6^th, 2010, 11:18am

You probably have to go in and create an internal node

module yourmod(mp, ...)
inout mp, ...;
electrical mp, ...;
electrical mp_int;

B = I(mp, mp_int) / area;

and then connect all the internal hierarchy to mp_int instead of mp.

Title: Re: port probes: VerilogAMS vs VerilogA
Post by Misha on Jul 8^th, 2010, 6:47am

Thank you for the suggestion. It does work. But the problem turned out to be slightly different. In a different location of the code I had the same line with an addition originating from the ahdllib code that I used as a base for my model:

Quote:

`ifdef __VAMS_ENABLE__
B = I(<mp>)/area;
`else
B = I(mp,mn)/area;
`endif

I guess it's a bug - the AMS simulator takes the first syntax but it actually is compliant with the second, same as the good old Spectre. I guess the Cadence's ahdllib was never QC'd with AMS simulator. Watch out for that VAMS_ENABLE macro :).

Thanks anyway for the advice,
Misha
Thanks