The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> typical PLL loop bandwidth range for clock multiplication. https://designers-guide.org/forum/YaBB.pl?num=1278673402 Message started by newic on Jul 9th, 2010, 4:03am

Title: typical PLL loop bandwidth range for clock multiplication. Post by newic on Jul 9th, 2010, 4:03am May I know what the typical PLL loop bandwidth range for clock multiplication. For example Clkref=100MHz, and clkout is 5GHz (50x) or 10GHz (100x)? Should the loop bandwidth always set to 1/10 of clkref regardless of clkout? Is it true? The lock time will be sluggish. Thank you in advance :)

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by raja.cedt on Jul 11th, 2010, 9:33am hi newic, it's not that simple man...it depends on that many things. For example if you are using ring oscillator and cleaner supply reference probably you can go with almost max bandwidth however you can choose lower bandwidth if are using LC vco and this discussion will go like any thing based on settling, Jitter......... Thanks, Rajasekhar.

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by loose-electron on Jul 11th, 2010, 12:32pm [quote author=newic link=1278673402/0#0 (50x) or 10GHz Should the loop bandwidth always set to 1/10 of clkref regardless of clkout? Is it true? The lock time will be sluggish. [/quote] 1/10 is a minimum to reduce any effects due to edge-to-edge induced modualtion General rule for frequency multipliers - as low as possible on BW. What determines how low? Lock time and jitter issues of course!

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by newic on Jul 12th, 2010, 3:07am the 1/10 criteria is mainly driven by the continuous time approximation from Gardner. My understanding: Ring osc has poorer phase noise compared to LC osc. It should use larger BW if possible to filter out vco phase noise whereas LC osc can use smaller BW to filter out more jitter due to input.   what is the BW range?? 100k~1MHz?

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by Mayank on Jul 13th, 2010, 1:58am Quote: what is the BW range?? 100k~1MHz? There is no Canonical Range for BW of a PLL. Tune it for your requirements. You can optimize PLL BW for Noise / Accumulated Jitter / Lock Time / Spurs & so on. For minimal Acc. Jitter / LockTime, you keep BW as high as possible while avoiding the complexity of Discrete Time Domain. For noise optimization on PLL BW, refer TextBooks & papers. Quote: the 1/10 criteria is mainly driven by the continuous time approximation from Gardner. Correct. 1/12 is safer but 1/10 is fine. I guess Jerry was talking about the synchronous jitter introduced from PFD-CP/FDN & other blocks when he was talking about edge-to-edge induced modulation. For a Generic Clock Multiplier, single period jitter is chiefly a spec. Hence, lower BWs are favourable. Optimize it acc. to your white noise & osc. phase noise in  your PLL. -- Mayank

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by vp1953 on Jul 13th, 2010, 2:56pm Hi Mayank, For minimizing cycle to cycle jitter, the BW should be as low as possible? Would not the same logic apply to accumulation jitter?

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by Mayank on Jul 15th, 2010, 1:50am Quote: For minimizing cycle to cycle jitter, the BW should be as low as possible? Yes, but what defines "POSSIBLE" in "as low as possible" --  VCO noise should not start dominating. Quote: Would not the same logic apply to accumulation jitter? No, acc. jitter is not generated in same way as short-term jitter. Acc. jitter mainly comes from autonomous blocks like VCO. Higher the PLL BW, faster is the correction of total jitter accumulating over a large period of time. Hence, higher BW provides lesser accumulated/long-term jitter. Accumulated jitter is heavily dependent on Comparison Frequency of the PLL as the time of accumulation is nothing but Tcomparison. --M

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by raja.cedt on Jul 15th, 2010, 6:14am hi mayank, 1. what do you mean by accumulated jitter is depends on comparison frequency? it is random jitter accumulated during pll open loop mode, so it's completely depends on vco phase noise and all. in the other way do you mean if you have lesser frequency then accumulated period is more?

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by vp1953 on Jul 15th, 2010, 8:54am Hi Mayank, Thank you for clarification. I now see what you mean. Accumulation jitter by its very definition of being an average over time represents low frequency component of the PLL phase noise. A higher loop BW results in lower close in phase noise - resulting in lower accumulation jitter : would you agree?

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by Mayank on Jul 15th, 2010, 10:01pm Quote: in the other way do you mean if you have lesser frequency then accumulated period is more? Exactly. Quote: Accumulation jitter by its very definition of being an average over time represents low frequency component of the PLL phase noise. Yes, accumulated jitter is a type of long-term period jitter, which is an average over time, which represents low-frequency part of Phase noise spectrum, but of the oscillator & not the in-band noise from CP/PFD/FDN/LF et al. Reason -- because only VCO jitter is accumulating jitter. Rest is synchronous/edge-to-edge jitter. Reason -- Because VCO jitter once introduced accumulates & gets corrected only after Tcomp, while edge-to-edge jitter from Driven Blocks like PFD/CP/FDN is a short term jitter whose rms value over a long-term is not so huge. Both accumulated Jitter from VCO + some rms contribution from E-to-E jitter of PFD/CP/FDN gets corrected at Tcomp. Quote: A higher loop BW results in lower close in phase noise - resulting in lower accumulation jitter : would you agree? Wrong. Close-In phase noise / InBand Phase Noise / Noise from PFD/CP/FDN/LF etc. is totally component dependent. There is an optimum pt. for BW where In-Band Noise cuts Osc. Pnoise. Any deviations in +- directions from that pt. will result in an increase in Jitter. --M

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by vp1953 on Jul 17th, 2010, 11:00am Hi Mayank, >Close-In phase noise / InBand Phase Noise / Noise from PFD/CP >/FDN/LF etc. is totally component dependent. >There is an optimum pt. for BW where In-Band Noise cuts Osc. Pnoise. >Any deviations in +- directions from that pt. will result in an increase in >Jitter. I am trying to map out what portion of the overall phase noise contributes to the accumulation jitter. Would the primary contributors to the accumulation jitter be from noise sources less than frequency f=1/Tcomparison?

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by loose-electron on Jul 17th, 2010, 1:45pm Cycle to cycle jitter is not just a function of loop BW You got a lot of second order issues that play into the problem.

Title: Re: typical PLL loop bandwidth range for clock multiplication. Post by love_analog on Jul 29th, 2010, 6:42am An intuitive way to look at it as follows Accumulated jitter is integration over all frequency. Large frequency typ becomes small so integration upper limit of 1G or 10G or 100G doesn't have much impact on final number. Now the question is low low to go. Obviously as you go lower and lower, you end up with infinite jitter. There are a few ways to resolve this a) some standards specify the lower limit. Lower than that is called wander, drift etc b) If measuring on RT scope, you will have finite memory depth. This will limit your lower frequency range

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