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Design >> Analog Design >> How long should bypass gate cap be?
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Message started by RobG on Jul 9^th, 2010, 9:23pm

Title: How long should bypass gate cap be?
Post by RobG on Jul 9^th, 2010, 9:23pm

I've always had a rule of thumb of not making gate caps longer than 10um. I have forgotten why, which happens more as I age. I think it was the n-well resistance that was in series with the cap. Anyone have a rule of thumb these days? I'm bypassing/decoupling power supplies in a 0.18u process and it would be better if I could use L=16u.

rg

Title: Re: How long should bypass gate cap be?
Post by neoflash on Jul 15^th, 2010, 10:54am

This is not a well-defined question.

The longer the channel the larger the ESR. But the tolerance should depend on your requirement.

Title: Re: How long should bypass gate cap be?
Post by ywguo on Jul 16^th, 2010, 2:42am

Yes, I agree with neoflash. The channel length or ESR depends on your requirement. Sometimes you even need larger ESR to kill the ringing caused by bonding wire.

Title: Re: How long should bypass gate cap be?
Post by RobG on Jul 16^th, 2010, 8:59am

Thanks for the feedback... I know it depends on the requirements, but what I'm not quite sure of is how would one create a model of a MOS cap that includes the effects of longer channel length. I do not think current models include this effect. Is it the Nwell resistance under the gate that causes the increase in ESR?

Title: Re: How long should bypass gate cap be?
Post by neoflash on Jul 16^th, 2010, 10:19am

If you are using nmoscap, the answer is yes. The nmos is the dominant source. (Some from the gate too.)

Title: Re: How long should bypass gate cap be?
Post by RobG on Jul 16^th, 2010, 11:08am

Actually I'm just using a pmos transistor since I'm not up to making a nmos over nwell cap. The rules are incredibly screwed up in this process and I have no time....

OK, that is what I thought. I just wanted to make sure it wasn't some funny physics... I was raised a bipolar man...

I just want to confirm.

Say you had a W=10, L=10 transistor with Cgs=10fF/um^2. Nwell sheet resistance is 1k-ohm/sq. The total cap would be 1pF and Res=1k. So a first order model would be three pmos (1/3pF) and two 500 ohm resistors (RC lumped element). The gates tied to vdd (ignoring poly R) and the sources would be distributed between the 500 ohm resistors: One going to the middle and the other two going to the ends which would be tied to vss.

Title: Re: How long should bypass gate cap be?
Post by neoflash on Jul 16^th, 2010, 11:28am

If a PMOS used and it is turned-on with bias condition, you don't worry about N-well resistance. Because the ESR consists of only the p-channel resistance and gate poly. N-well is shielded by the channel so no impact on the ESR.

Title: Re: How long should bypass gate cap be?
Post by RobG on Jul 16^th, 2010, 12:00pm

lol... I just looked it up in razavi's book, page 622. It is just channel resistance ~1/gm and the time constant is proportional to L^2.

Title: Re: How long should bypass gate cap be?
Post by neoflash on Jul 16^th, 2010, 12:04pm

No. It is not related with gm, instead it is propotional to gds.

Title: Re: How long should bypass gate cap be?
Post by RobG on Jul 16^th, 2010, 12:36pm

gm is a little low for a device with no dc current, eh? ~1/L/(Vgs-Vt) is what I was getting at. I'm doing layout which means I can, and did, leave my brain at home.

Anyway, why is this different for an nmos in an Nwell?