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Design Languages >> Verilog-AMS >> A verilogA code to measure frequency
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Message started by casual on Jul 9^th, 2010, 11:15pm

Title: A verilogA code to measure frequency
Post by casual on Jul 9^th, 2010, 11:15pm

A verilogA code to measure frequency (copied from designers-guide)

However, i got many warnings and errors.
Is it because it is a verilogAMS rather than verilogaA?
I am using Cadence 5141 mmsim61

1) like the `timescale 1ns / 1ps ->

Warning from spectre during SpectreHDL compile.
"xxxx/freq_meas/veriloga/veriloga.va", line 6:
Warning: `timescale directive is found in the module, if without a
`default_transition directive or local setting of transitions in either
transition filters or Z-transforms. In Verilog-A this results in the
`timescale setting the transistion time which is not supported by the
Verilog-AMS LRM. Please use `default_transition instead to set default
transition time for transition filters or zi_* filters.

Sound like I could I use this command.

2)
Line14 "initial begin<<--?" syntax error

Code:

`timescale 1ns / 1ps

module freq_meas (clk);
input clk;
real last_time, current_time, freq;

initial begin
last_time = 0.0;
freq = 0.0;
end
always @(posedge clk) begin
current_time = $realtime;
if (last_time > 0.0)
freq = 1.0e9 / (current_time - last_time);
last_time = current_time;
end
endmodule

Title: Re: A verilogA code to measure frequency
Post by casual on Jul 10^th, 2010, 1:46am

I know the issue. It is a verilogAMS code and not the verilogA code.

I have eventually made it in verilogA to measure frequency... :)

Title: Re: A verilogA code to measure frequency
Post by Geoffrey_Coram on Jul 12^th, 2010, 6:01am

Quote:

Warning from spectre during SpectreHDL compile.

Seems like you incorrectly included it in the netlist, so that Spectre thinks it is SpectreHDL, not Verilog-A nor Verilog-AMS.

Title: Re: A verilogA code to measure frequency
Post by Marq Kole on Jul 12^th, 2010, 7:40am

Spectre has no separate statements for including SpectreHDL or Verilog-A. The ahdl_include statement will do either.

Also with the latest version of Spectre in MMSIM you will get the above results (although none of the versions I've tested -- 5.1, 6.1, and 7.2 -- say something about SpectreHDL - they all say:
"Warning from spectre during AHDL read-in."
)

The warning may suggest that the timescale directive is supported in Spectre Verilog-A, but in reality that is not the case. However, it is a warning as Spectre is still able to continue and make a successful simulation, but not taking this directive into account.

Marq