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Modeling >> Behavioral Models >> clock generator in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1279443095

Message started by bsaqycx on Jul 18^th, 2010, 1:51am

Title: clock generator in Verilog-A
Post by bsaqycx on Jul 18^th, 2010, 1:51am

Now I need a clock generator model. Its function is to firstly detect the freq of input clock and then creat & output the clock with the same freq ( the duty-cycle of the output should be 50%). What'a more, the generator has disable pin "dis" which means the output would be zero if the dis is high.

My model is like below:
model clk_gen (in,out,vdd,vss);
input in; electrical in;
input vdd; electrical vdd;
input vss; electrical vss;
output out;electrical out;
parameter real tr=1e-10;
parameter real tf=1e-10;
parameter real td=2e-9;
real freq, current_time, last_time, next, vh, vl ,vth;
integer m;

analog begin
vh= V(vdd);
vl= V(vss);
vth= 0.5*(vh+vl);

@(initial step) begin
freq = 0;
next= $abstime;
last_time = 0;
end

@(cross(V(in)-vth,1)begin
current_time= $abstime;
if ( last_time >0) freq= 1/(current_time-last_time);
last_time= current_time;
end

@timer(next) begin
m=!m;
next= 0.5/freq + next;
end
V(out) <+ transition (n!vh:vl,td,tr,tf);
end
end
end module

However, I couldn't get the waveform I expect and I think the problem may come from the time function. Pls help me and thx in advance!

Title: Re: clock generator in Verilog-A
Post by bsaqycx on Jul 18^th, 2010, 9:23pm

I've modified the code as you suggest but the waveform is still not desired. Pls help and thx!

Title: Re: clock generator in Verilog-A
Post by bsaqycx on Jul 18^th, 2010, 10:23pm

module led_fb_slicer(clk_out, clk_in, ibias_buf_n10u, ibias_n_2u, led_driver_off, vdd, vss);
output clk_out;
electrical clk_out;
input clk_in;
electrical clk_in;
input ibias_buf_n10u;
electrical ibias_buf_n10u;
input ibias_n_2u;
electrical ibias_n_2u;
input led_driver_off;
electrical led_driver_off;
input vdd;
electrical vdd;
input vss;
electrical vss;
parameter real tr = 1e-10 from [0:inf);
parameter real tf = 1e-10 from [0:inf);
parameter real td = 2e-9 from [0:inf);
real vh, vl, vth, state, last_time, current_time, freq, next;
integer n, en, dis;

analog begin
@(initial_step) begin
next=$abstime;
last_time = 0;
freq = 0;
n = 1;
en=0;
dis=1;
vh = V(vdd);
vl = V(vss);
vth = 0.5*(vh+vl);
end

@(cross(V(clk_in) - vth, 1, ,1e-12 ,dis)) begin
current_time = $abstime;
if (last_time > 0.0)
freq = 1 / (current_time - last_time);
last_time = current_time;
end

if (freq>0)begin
en=1; dis= 0;
end

@(timer(next,,3e-10,en))begin
n = !n;
next = 0.5/freq +next;
end
state= (V(led_driver_off) < vth);
V(clk_out) <+ transition ((state && n)? vl:vh,0,tr,tf);

end

endmodule

Now I use the "enable" function to control timer and cross, but sorry, there's still some parser errors.

Thx

Title: Re: clock generator in Verilog-A
Post by Ken Kundert on Jul 18^th, 2010, 11:57pm

You cannot put a transition function inside an @ block.

It would be helpful when quoting code to use the "Insert Code" button (the button marked with #) so that we can see the indenting. I also have to say that it is very difficult to help you as you don't really say what is wrong except in the vaguest of terms and you mention parser errors, but do not say what they are.

-Ken

Title: Re: clock generator in Verilog-A
Post by bsaqycx on Jul 19^th, 2010, 12:54am

sorry, I'm a new comer here and I'll take your advice next time.