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Design Languages >> Verilog-AMS >> how to implement solver with digital outputs
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Message started by Ari on Jul 20^th, 2010, 6:08am

Title: how to implement solver with digital outputs
Post by Ari on Jul 20^th, 2010, 6:08am

I am trying to implement in Verilog-A something doable with standard analogLib cells.

I wish to implement Verilog-A cell with two inputs: vin,vref and digital output bus :vsel[5:0] (fig. A)

The cell should set vsel[5:0] control bits such that vin-vref is minimal.
vsel[5:0] connects/disconnects 6 resistor finger (monotonically increasing in size), by than changing vin.

While it is relatively easy to implement such cell in analogLib cell, using successive approximation method, I was unsuccessful implementing it in Verilog-A.

To make my point clear : had the variable resistor been continuous varistor (fig. B), it would be easy to implement such controller through the implicit assignment:
V(vout) : V(vin)=V(vref)

Any ideas on how to implement such discrete controller (successive approximation or other method), and general suggest a method for discrete optimization?

Regards,

Ari

Title: Re: how to implement solver with digital outputs
Post by boe on Jul 20^th, 2010, 9:50am

Ari wrote on Jul 20^th, 2010, 6:08am:

...
While it is relatively easy to implement such cell in analogLib cell, using successive approximation method, I was unsuccessful implementing it in Verilog-A.

If you can build it with analogLib cells, you could build a hierarchical Verilog-A model instantiating the analogLib cells you need.

Quote:

To make my point clear : had the variable resistor been continuous varistor (fig. B), it would be easy to implement such controller through the implicit assignment:
V(vout) : V(vin)=V(vref)
...
Any ideas on how to implement such discrete controller (successive approximation or other method), and general suggest a method for discrete optimization? ...

For monotonic dependency, I would do a binary search.

It would help if you could give a bit more information (see also Forum guidelines):
What did you do that did not work? Can you post the code? What type of simulations do you want to perform? What effects do you want to model? Which simulator do you use (Spectre?)? ...

BOE

Title: Re: how to implement solver with digital outputs
Post by Ari on Jul 21^st, 2010, 2:11am

Boe,

Thank you for your reply.

Since I have analogLib implementation, I am more interested at the capabilities of Verilog-A, rather than getting it implemented. I always through Verilog-A can do better than standard analogLib structures, but now I am skeptic.

I am attaching the schematics of the analogLib implementation. As you can see, I use several instances of the discrete varistor to perform the binary search.

As for my Verilog-A attempts, I would like to have something like this, which is totally illegal in Verilog-A...

Code:

for(i=2;i<=0;i=i+1) begin
res_ctlr[i]=1;
//we would like that res_ctrl_int[i] will propagate outside, changing the resistor value, by that affecting fb_in
res_ctrl[i] = V(fb_in) > V(vref);
//we would like that between each iteration loop, value of res_ctrl will propagate outise, affecting fb_in, all within DC computation !
end

Title: Re: how to implement solver with digital outputs
Post by boe on Jul 21^st, 2010, 4:49am

Ari,
Using several instances of dividers, you could of course replicate this in Verilog-A. Another possibility is to feed bus of all taps of the resistive divider to the Verilog-A model.
Trying to use one resistive divider and run an instantaneous search over the digital control signals for every simulation time point without access to internal states is unphysical (i.e. you cannot do this in reality) anyway.
If you want to model a successive approximation algorithm you need some kind of timing/clock (timer event or external clock): After every clock you do a comparision, change the output until algorithm converges.
BOE
PS: You could also exploit knowledge of the divider characteristics in your Verilog-A controller.
PPS: Does this help?

Title: Re: how to implement solver with digital outputs
Post by Geoffrey_Coram on Jul 21^st, 2010, 5:11am

Ari wrote on Jul 21^st, 2010, 2:11am:

As for my Verilog-A attempts, I would like to have something like this, which is totally illegal in Verilog-A...

Code:

for(i=2;i<=0;i=i+1) begin

That for-loop doesn't make any sense...

I'm still not entirely clear on what you are trying to do: the original schematic looked like you wanted the Verilog-A module to set some control bits, but I don't understand how those bits would affect the resistor. Are you intending to write the resistor in Verilog-A also?

It sort of seems like you are writing an ADC -- taking the analog vref and converting it to a set of digital bits that set the resistor; you just happen to use the resistor to then generate vin.

Title: Re: how to implement solver with digital outputs
Post by Ari on Jul 21^st, 2010, 6:31am

Hi,

My hope was to avoid the multiple instantiation when using Verilog-A.
I thought I could propagate the intermediate values within the DC operating point internal stage.

So, in the current situation, I am left with the following clumsy code:

Code:

// VerilogA for ari_veriloga_behave, SA_controller, veriloga

`include "constants.vams"
`include "disciplines.vams"

`define NUM_OF_BITS 3
module SA_controller(ref_in,fb_in,sel_out_inst0,sel_out_inst1,sel_out_inst2,sel_out_final);

// digital select bits. it is assumed that :
// 1. When high fb_in value reduces
// 2. Effect of sel_out bits on fb_in is monotonically, i.e. chnage of sel_out[0] has less or equal effect comparing to sel_out[1], and so forth
output [`NUM_OF_BITS-1:0] sel_out_inst0 ;
output [`NUM_OF_BITS-1:0] sel_out_inst1 ;
output [`NUM_OF_BITS-1:0] sel_out_inst2 ;

output [`NUM_OF_BITS-1:0] sel_out_final;
//feedback voltage from each of the NUM_OF_BIT instances connected to sel_out
input [`NUM_OF_BITS-1:0] fb_in ;

//reference voltage=target voltage
input ref_in;

voltage ref_in;
voltage [`NUM_OF_BITS-1:0] fb_in;
voltage [`NUM_OF_BITS-1:0] sel_out_inst0 ;
voltage [`NUM_OF_BITS-1:0] sel_out_inst1 ;
voltage [`NUM_OF_BITS-1:0] sel_out_inst2 ;
voltage [`NUM_OF_BITS-1:0] sel_out_final ;

//logic high/low level for output
parameter real vout_high=1 from (-inf:inf);
parameter real vout_low=1 from (-inf:inf);

genvar i;
real comp_out[`NUM_OF_BITS-1:0];

analog begin

for(i=0;i<`NUM_OF_BITS;i=i+1) begin
if(i<`NUM_OF_BITS-1)
V(sel_out_inst2[i]) <+ vout_low;
else
V(sel_out_inst2[i]) <+ vout_high;
end//for
comp_out[2]=V(fb_in[2]) > V(ref_in) ? vout_high : vout_low;

for(i=0;i<`NUM_OF_BITS;i=i+1) begin
if(i<`NUM_OF_BITS-2)
V(sel_out_inst1[i]) <+ vout_low;
end//for
V(sel_out_inst1[`NUM_OF_BITS-2]) <+ vout_high;
V(sel_out_inst1[`NUM_OF_BITS-1]) <+ comp_out[`NUM_OF_BITS-1];
comp_out[1]=V(fb_in[1]) > V(ref_in) ? vout_high : vout_low;

for(i=0;i<`NUM_OF_BITS;i=i+1) begin
if(i<`NUM_OF_BITS-3)
V(sel_out_inst0[i]) <+ vout_low;
end//for
V(sel_out_inst0[`NUM_OF_BITS-3]) <+ vout_high;
V(sel_out_inst0[`NUM_OF_BITS-2]) <+ comp_out[`NUM_OF_BITS-2 ];
V(sel_out_inst0[`NUM_OF_BITS-1]) <+ comp_out[`NUM_OF_BITS-1 ];
comp_out[0]=V(fb_in[0]) > V(ref_in) ? vout_high : vout_low;

for(i=0;i<`NUM_OF_BITS;i=i+1) begin
V(sel_out_final[i])<+comp_out[i];
end//for

end//analog
endmodule

`undef NUM_OF_BITS

any ideas on how to make this code a bit more elegant?

Title: Re: how to implement solver with digital outputs
Post by boe on Jul 21^st, 2010, 7:34am

Ari,
For a asynchronous solution I'd try somethig like:

Code:

module control(ref_in, rtap_in, sel_out);
input ref_in;
input [7:0] rtap_in;
output [2:0] sel_out;

voltage ref_in;
voltage [7:0] rtap_in;
voltage [2:0] sel_out;

integer i,j;
analog begin
j = 0;
for (i=0; i < 8; i=i+1) begin
if (V(rtap[i])<V(ref_in)) j = j + 1;
end
V(sel_out[2]) <+ transition( (j>3)?vout_high:vout_low , ...);
V(sel_out[1]) <+ ...
...
end

Of course, you need all comparator thresholds (rtap_in) as inputs for such a model.
BOE
PS: This is the lazy implementation, you could of course add binary search.

Title: Re: how to implement solver with digital outputs
Post by Ari on Jul 21^st, 2010, 8:37am

Boe,

I think you code is missing something :

1. The number of taps should be equal to the number of select bits. We duplicate the divider N times (2^N is the divider resolution) each instance decides on single bit.
Therefore rtap_in should be :

Code:

input [7:0] rtap_in;

2. You should also have N duplicates of the select outputs, each controlling one of the dividers.

As for your last comment : I think my implementation is based on binary search. Was that what you were referring to ?

Thanks,

Ari

Title: Re: how to implement solver with digital outputs
Post by boe on Jul 21^st, 2010, 10:29am

Ari,
Your approach is a pipelined binary weighted approach generating 1 bit per divider.

I suggested a flash approach: compare input signal to all signal thresholds and translate resulting thermometer code to binary weighted result. You could also modify this to a successive approximation approach by adding some event control and an iterative binary search over the code space.

Since I don't know what you want to model, I cannot propose the "right" solution for your problem...

I referred to binary search in order to point out implementation options of conversion to binary coded output.
BOE

Does this help?

Title: Re: how to implement solver with digital outputs
Post by Ari on Jul 21^st, 2010, 1:47pm

Boe,

First - thank you !

Let's see if I understand you correctly : in your flash implementation you need 2^N (N number of divider control bits) instantiation of the divider, each with different hard wire select bits.
In this implementation, there is not loop : you just iterate through the different instances (each with its select bits) till you find the 1st tap which is lower than vref (you assume monotonicity, of course)

While this approach uses very elegant and small Verilog-A code, it affects dramatically the OP calculation when N is large.

Am I correct ?

I am still bothered with the question whether implicit function can be used in such case, avoiding the multiple instance of the divider. ..

Thanks again,

Ari

Title: Re: how to implement solver with digital outputs
Post by boe on Jul 22^nd, 2010, 7:04am

Ari,
No, I'd use one divider consisting of 2^N resistors (resistor string) creating 2^N output voltages (I assume this is what you use in your controllable divider anyway). Just instead of using switches to select one voltage I'd output all of them and compare each to the input voltage.
Such a resistor string is inherently monotonic, so I used this in the decoder.

BOE
(Added) PS: If you use another topology, you can of course adapt the code accordingly.
PPS: What kind of ADC do you want to model?

Title: Re: how to implement solver with digital outputs
Post by boe on Jul 22^nd, 2010, 10:06am

Ari,
One more thing: If you want to do successive approximation with only one divider, you need some kind of clock/timing to define sequence of operations (for each bit set reference, settling, compare).
This can be done using either external clock and cross event or using timer event (internal clock).
BOE