The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Minimize offset voltage at inputs of comparator.. help needed
https://designers-guide.org/forum/YaBB.pl?num=1279737751

Message started by kanu on Jul 21^st, 2010, 11:42am

Title: Minimize offset voltage at inputs of comparator.. help needed
Post by kanu on Jul 21^st, 2010, 11:42am

We need to design a comparator which has a switching voltage of 1mV. As of now, the offset required between the two inputs is 4mV. How should I go about reducing this to 1mv? Further, I have a doubt here.. won't the supply noise or process variation affect this offset voltage ?

Thanks,
Kanu

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by AnalogDE on Jul 21^st, 2010, 4:09pm

To get a 4x reduction in the offset voltage you need to scale up your existing circuit by a factor of 16X. Power will also scale by 16X.

You can also look up offset cancellation schemes by looking up papers by Razavi. A good introductory source is his book, "Principles of Data Conversion System Design"

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by kanu on Jul 21^st, 2010, 5:29pm

One more question.. I was just wondering will it be good idea to design opamp for this comparator instead of using a comparator circuit ? What I mean to ask is that since both comparator and opamp have input stage of differential amplifier... will I require to scale opamp too by 16X ?

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by vp1953 on Jul 21^st, 2010, 7:24pm

Hi Kanu,

How did you determine that the offset voltage is 4mV?

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by kanu on Jul 21^st, 2010, 8:45pm

I applied voltages of 0.604V and 0.6V to the two inputs of the differential amplifier of the comparator (though I guess.. this is not enough and I will need to run monte carlo simulation to say for sure). What actually I mean is that our project needs higher sensitivity for the comparator, ie, it should be able to detect the difference between the inputs which is as low as 1mV. Do correct me if you think that my methodology is incorrect.

For the comparator circuit, I actually used one of the comparator circuit given in Dr. Baker's book. I modified it to work for 1.2V supply and 90nm. Finally, the circuit consumes power of 320uW (which I may need to reduce further..probably by compromising on current and slew rate)

Further, as mentioned in above post I increased Ws by 4 times of input transistors. It did take switching voltage down to 2mV without considerable increase in power.

Now, as mentioned in the book I was trying to increase the transconductance of the input transistors to see the effect ( I am not sure how is it going to affect the power though).

I will appreciate if I can get any help.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by raja.cedt on Jul 21^st, 2010, 9:15pm

hi,
its hard to get 1 or 2mv offset with analog techniques..try with digital calibrations.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by kanu on Jul 21^st, 2010, 9:50pm

So, does that mean even opamp isn't good enough ? Is this because of process variation and supply voltage noise ? or its only that 1mV offset is not possible along with low power ? Please suggest something. I think I am lost :(

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by sheldon on Jul 22^nd, 2010, 5:58am

Kanu,

In general, op amps are not intended to operate "slammed" into the
rail. They often do not recover well from this condition. Next, you
need to be careful, there are two terms to offset: systematic and
random. You seem to saying that the systematic offset is 4mV when
you need a resolution of 1mV. So you have a big problem, you need
to improve the balance in your design so the systematic offset is
much smaller than the required resolution, ~100uV. Then you need to
run Monte Carlo to determine the random offset. As Raja noted, you
probably need to look at circuit techniques to eliminate random offset,
after eliminating the systematic offset. If the process has bipolars
you might want to try them, some nice 1 mil circular emitter might
get you the offset that you need if you can live with the base current
and lower ft.

Best Regards,

Sheldon

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by raja.cedt on Jul 22^nd, 2010, 6:58am

hi, what i mean is in analog compensation you have to put into loop and store some where in a cap and subtract in the next phase. Where as in digital calibration you will blindly pump some programmable current and make both legs of diff pair balanced with this you will get very nice control across Monte Carlo also. I have implemented this in one my work. if you want to see basic implementation refer the following pap (i have written this)

High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique

Thanks,
rajasekhar.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by vp1953 on Jul 22^nd, 2010, 11:16am

Hi Kanu,

Process gradients to contribute to random offset, can be minimized with proper layout (check Razavi, CMOS Analog Design, Last chapter I think).

Check out "correlated double sampling" for minimizing 1/f noise, offsets

many CMOS process provide low ft npn's and maybe that is option for the input stage

lastly if your output is not being railed, and if the frequency of your signal is large (say several 100k Hz), you might still get away with a large offset voltage with proper filtering etc. The offset voltage varies slowly

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by kanu on Jul 22^nd, 2010, 11:53am

I see.. I get the problem. I did some reading on systematic and random offsets. I will try to reduce systematic offset.

Raja, I will appreciate if you can send me your paper. I tried to access through our online library but could not get it.

Thanks all for help.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by raja.cedt on Jul 22^nd, 2010, 9:22pm

please send your mail id..

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by Alexandar on Jul 23^rd, 2010, 12:18am

May I ask why analog techniques are not good enough to get to 1mV offset?

It is true that you have to think of influence of charge injection/CLK feedthrough of the switches that are connected to a sampling capacitor. However, these are not random offsets any more, right?

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by raja.cedt on Jul 23^rd, 2010, 12:38am

hi alexander..what i mean to say is across corner your switch resistance may change or switch vds may change or while connecting from sample mode to hold mode also some leakage may happen and remember all this things will come into picture once you targeted for tiny offsets like 1mv,.5mv....

Thanks,
Rajasekhar.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by thechopper on Jul 23^rd, 2010, 7:24pm

IF chopping is used instead of CDS or AZ residual offsets as low as 20uv can be achieved. This is way smaller than 1mv.
Commercial autozero opamps (which are chopper stabilized and not autozero really) have actually those input referred offset.
So 1mv is can be way reduced with analog techniques like chopper stabilization.

Best
Tosei

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by loose-electron on Jul 24^th, 2010, 11:08am

Lex wrote on Jul 23^rd, 2010, 12:18am:

May I ask why analog techniques are not good enough to get to 1mV offset?

What you got going on here is 5 different people
saying you can use 5 different methods to do the same thing.

That said - there are multiple ways to get this done.

Geometry scaling (big devices and better matching) will only work up to a point. You need the specific matching data for the foundry process to tell you if this is viable.

The 16X increase to get better matching is an academic perception that is not valid, because it is based upon a number of older papers that are no longer valid at smaller geometry.

Static offset compensation thru a digital adjustment works.
Dynamic compensation with capaciive offset cancellation works too.

The quick decision between the above two is whether or not its a clocked system. Sampled time systems lend themselves well to doing dynamic offset cancellation.

OP-amps make poor comparators. You are gain-BW response limiting the device so it can work inside a feedback loop. Not needed in a comparator.

As for the signal you need to respond to? Sounds like you need more gain in the system.

There are lots of papers and books out there on this subject.
Time to do some research.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by kanu on Jul 24^th, 2010, 1:25pm

Hi loose-electron,

Thanks for your reply. This makes picutre a little clearer for me.

First of all, my system is not a clocked one. So I think I will have to use dynamic offset cancellation technique.

Further, it may sound naive. But I am asking this just to confirm if I got everything right. I was wondering, as in an opamp basically compensation capacitor is used to make it stable for high frequency operation (and such that it works in feedback loop)... so why not I just use bias circuit + differential amplifier + common source + push pull amplifier to make my comparator ? Also, I plan to use capacitor for offset cancellation. Do you see any problem with this circuit (our aim is design a comapator which can just detect difference as low as 1mV) ?

Thanks,
Kanu

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by love_analog on Jul 29^th, 2010, 6:58am

Kanu
I don't understand how you can say you are using cap for offset cancellation and also say that you don't have any clocks.

I presume you are using cap to store the offset voltage in 1 phase of the clock and in the next phase you cancel that "stored" offset from the real signal.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by kanu on Jul 29^th, 2010, 7:22am

Hi love_analog,

My mistake.. I realized it after posting the above reply. Yes, right now as you said I am trying to implement autozeroing for offset calculation for 2-stage opamp design. But for some reasons it is not giving me expected output. So I just wanted to verify following doubts:

- Is unity gain stability necessary for autozero to work properly?
- What exactly tells me the speed of the circuit ? Is it slew rate or propagation delay ? I understand that slew rate gives the rate at which the load capacitor it being charged and discharged. I mean to ask which parameter, slew rate or propagation delay should be right measure for speed of a comparator circuit?

I appreciate everyone has been a lot of help to me on this thread. I am able to proceed till autozeroing because of this.

Thanks and Regards,
Kanu

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by thechopper on Aug 4^th, 2010, 4:58am

Hi

kanu wrote on Jul 29^th, 2010, 7:22am:

- Is unity gain stability necessary for autozero to work properly?

Ususally YES. You have to set the amplifier in unity gain to measure and store the input (and output in this case) referred offset. To measure such offset you will need a stable opamp.

kanu wrote on Jul 29^th, 2010, 7:22am:

- What exactly tells me the speed of the circuit ? Is it slew rate or propagation delay ? I understand that slew rate gives the rate at which the load capacitor it being charged and discharged. I mean to ask which parameter, slew rate or propagation delay should be right measure for speed of a comparator circuit?

Both will contribute to the total response time of the circuit.

Best
Tosei

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by raja.cedt on Aug 4^th, 2010, 9:36pm

hi kanu,

adding to Tosei post not only unity gain stability but settling time is very important (it should settle with in sample period)

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by Alexandar on Aug 5^th, 2010, 3:52am

raja.cedt wrote on Aug 4^th, 2010, 9:36pm:

hi kanu,

adding to Tosei post not only unity gain stability but settling time is very important (it should settle with in sample period)

Because of the unity gain, an amplifier is much faster than in normal operation. So I wouldn't expect settling time to be the limiting factor.

Title: Re: Minimize offset voltage at inputs of comparator.. help needed
Post by thechopper on Aug 5^th, 2010, 6:00pm

Lex wrote on Aug 5^th, 2010, 3:52am:

Because of the unity gain, an amplifier is much faster than in normal operation. So I wouldn't expect settling time to be the limiting factor.

It is in fact important since if settling time is not enough, then stored offset value will not be the actual offset value of the amplifier and cancellation efficiency will be degraded.

Best
Tosei