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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> VerilogA into Device Netlist https://designers-guide.org/forum/YaBB.pl?num=1280393397 Message started by e.fisher on Jul 29th, 2010, 1:49am |
Title: VerilogA into Device Netlist Post by e.fisher on Jul 29th, 2010, 1:49am Hello. Quick query. I have an extracted net list of a semiconductor pn junction device, i.e. the net list of the extracted capacitances, bulk resistances etc. The device is DRC and LVS clean but does not include the devices behaviour. I have a separate VerilogA electrical behavioural model of the device which takes in a generic trigger pulse and gives the correct (verified) behaviour at its anode and cathode. Of course If I put both into schematic the block will no longer LVS as the VerilogA is essentially not there. Instead I want to add the VerilogA model into net list, preferably with code to only simulate if in electrical simulation mode rather than LVS or DCR modes. The VerilogA prototype is: module GeigerModel(PLUS, MINUS, PULSE) Thanks very much. Ed Fisher |
Title: Re: VerilogA into Device Netlist Post by Geoffrey_Coram on Jul 29th, 2010, 5:29am You probably need to tell us what tools you're using. Some tools generate a different netlist for LVS than for Spice simulation; I think Cadence has some sort of "hierarchy editor" that allows you to substitute behavioral models for various blocks, etc. |
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