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Design Languages >> Verilog-AMS >> Verilog-A code for charge pump
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Message started by vp1953 on Jul 29^th, 2010, 4:14pm

Title: Verilog-A code for charge pump
Post by vp1953 on Jul 29^th, 2010, 4:14pm

I am looking for verilogA code to implement a charge pump (used in PLLs). The default code available in Cadence seems to be very unrealistic in that even when the output voltage is at ground or supply, current continues to be sunk/sourced resulting in substantial build of voltage.

I did not find any code for a charge pump at the designers guide site (it has code for pretty much everything else).

Thank you in advance!

Title: Re: Verilog-A code for charge pump
Post by Ken Kundert on Jul 31^st, 2010, 10:38am

Take a look at http://www.designers-guide.org/VerilogAMS/functional-blocks/pfd_cp/pfd_cp.va. I have updated the PFD/CP on this site to include an output clamp that limits the output voltage to the rails.

-Ken

Title: Re: Verilog-A code for charge pump
Post by vp1953 on Aug 2^nd, 2010, 11:25am

Hi Ken,

Thanks a million! It is greatly appreciated.