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Simulators >> Circuit Simulators >> Simulation Accuracy in veriloga (hspice) for very low jitter synthesizer
https://designers-guide.org/forum/YaBB.pl?num=1282069033

Message started by neoflash on Aug 17^th, 2010, 11:17am

Title: Simulation Accuracy in veriloga (hspice) for very low jitter synthesizer
Post by neoflash on Aug 17^th, 2010, 11:17am

Hi,

I met one challenge in simulating the low jitter synthesizer in verilogA in hspice simulator.

The theoretical rms jitter of the synthesizer is expected to be 30fs. However, the accuracy of the simulator is somehow limited to be at ps level.

How can I further improve the simulation accuracy for this verification?