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Design Languages >> Verilog-AMS >> Verilog A ladder
https://designers-guide.org/forum/YaBB.pl?num=1282368051

Message started by Streamcx on Aug 20^th, 2010, 10:20pm

Title: Verilog A ladder
Post by Streamcx on Aug 20^th, 2010, 10:20pm

I`m starting with Verilog A.

I need "ladder" from 0V to -2.04V with step 0.008 V (step can be smaller), 256 time intervaks.

I have this code (not my):

Code:

`include "disciplines.vams"

module ladder (outp,outm);
output outp,outm;
electrical outp,outm;

// extent of the signal output
parameter real vmin=0;
parameter real vmax=2.56;
// number of steps in the "ladder"
parameter integer maxcount=256;
// is it periodic? Set to 0 if you want it to be one shot
parameter integer periodic=1;
// period of time between steps in the ladder
parameter real period=10n;
// rise, fall, and delay of each step
parameter real tr=0.1n;
parameter real tf=0.1n;
parameter real td=0;

// internal variables
real scale;
integer count;

analog begin
@(initial_step) begin
count=0;
scale=(vmax-vmin)/(maxcount-1);
end

@(timer(period,period))
if(periodic) count=(count+1)%maxcount;
else count=min(count+1,maxcount-1);

V(outp,outm) <+ transition(count*scale,td,tr,tf);
end

endmodule

I set Vmax=0, Vmin=-2.048. Why when time increase signal go down from 0, to -2.048 (like I need).
Why this is not go up from 0 to 2.048?

Title: Re: Verilog A ladder
Post by Ken Kundert on Aug 21^st, 2010, 12:30am

At first glance, the code looks okay. Any chance you simply wired the component into the circuit backward by accidentally flipping the terminals?

-Ken