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Modeling >> Semiconductor Devices >> pMOS gate capacitance
https://designers-guide.org/forum/YaBB.pl?num=1282818865

Message started by Godfrey on Aug 26^th, 2010, 3:34am

Title: pMOS gate capacitance
Post by Godfrey on Aug 26^th, 2010, 3:34am

Im getting myself confused, Im using a pMOS cap (s/d to Vdd) but after extraction, see a very large capacitance from gate to Vss?

Every node of the cap is over the Nwell, so shouldn't the parasitic capacitance be all w.r.t Vdd? I would expect some capacitance to ground for the connection to the structure but Ive removed that.

Title: Re: pMOS gate capacitance
Post by carlgrace on Aug 26^th, 2010, 4:23pm

Are you extracting with a "lumped C" algorithm, where all the parasitic caps are lumped and shorted to ground? I have seen this done to simplify the extraction, but it sometimes leads to weird stuff like you have seen.

Title: Re: pMOS gate capacitance
Post by Godfrey on Sep 1^st, 2010, 9:21am

Yes, it turns out that was the problem. The extraction finds the cap but connects it to Vss rather than Vdd.

Do all extraction tools behave like this?

Title: Re: pMOS gate capacitance
Post by vivkr on Sep 2^nd, 2010, 7:04am

Godfrey wrote on Sep 1^st, 2010, 9:21am:

Yes, it turns out that was the problem. The extraction finds the cap but connects it to Vss rather than Vdd.

Do all extraction tools behave like this?

Alas! they do, more often than not. But there is always a option somewhere permitting you to extract the caps in a "coupled" mode so that they are added between each 2 nets. The problem arises if you of course choose the default mode "cap to ground" or whatever it it called in your extraction setup.

I have never understood why the tools need to be this absurdly set up. After all, in any serious analog design (and you wouldn't be extracting parasitics if you were not serious), you need to know where the caps are pointing to. Maybe logic designers don't care about that.

And even if there is an option for extracting caps to ground, then atleast one might have an option for defining the various "grounds", i.e. the various supply and ground nets so that all caps from signal nodes to these are preserved, and other caps are merged to the relevant "ground".

Perhaps someone from the EDA community can throw some light on this. Seems like some relic from the past...

Vivek

Title: Re: pMOS gate capacitance
Post by Alexandar on Sep 3^rd, 2010, 2:09am

Your analog design should be robust against parastics from the start. So extracting parastics for every analog design? As verification yes, but as part of the design.... only for the really demanding ones I guess.
I would say, if parastics play a big role in your design, make simple models beforehand and design by those.