The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> recursive async. decoder / triggering user events
https://designers-guide.org/forum/YaBB.pl?num=1283805601

Message started by Ari on Sep 6^th, 2010, 1:40pm

Title: recursive async. decoder / triggering user events
Post by Ari on Sep 6^th, 2010, 1:40pm

I wish to implement async gray->binary decoder, according to the following rule (G=gray bit, B=equivalent binary bit):
B<n> = G<n>
B<n-1> = G<n> ^ G<n-1>
B<n-2> = G<n> ^ G<n-1> ^ G<n-2>
....

I thought of the following clumsy code:

Code:

@(initial_step or cross(V(gray[4])-0.5,0))
bin_int[4] = V(gray[4])>0.5 ? 1 : 0;

for(i=3;i>0;i=i-1) begin
@(initial_step or cross(V(gray[i])-0.5,0) or cross(V(bin[i+1])-0.5,0)) begin
bin_int[i] = V(gray[i])>0.5 ? 1-bin_int[i] : bin_int[i]; //XOR
end@(initial_step ....
endfor

create events on binary value changes
for(i=0;i<=4;i=i+1)
V(bin[i])<+bin_int[i];

However, I don't like this code for two reasons :
1. I used redundant electrical bin nodes to spawn event upon update of some binary bit. Otherwise, the recursion will not work.
2. Solution in operating point is wrong since teh above mention trick does not spawn events

Code:

bin[4] <+ V(gray[4])>0.5 ? 1 : 0;

for(i=3;i>0;i=i-1) begin
bin[i] = V(gray[i])>0.5 ? 1-(V(gray[i+1])>0.5 ? 1 : 0) : (V(gray[i])>0.5 ? 1 : 0);
end//for

I don't like the latter idea since it lacks events at all, which I think is ineffective in simulation time and event prone to bugs in the simulator.

I would like to hear your opinion about these two implementations, or any suggestion on how to implement such async decoder.

Also, I am very curious why user events are not supported in Verilog-A. I think event triggering can resolve the operating point of solution 1

Ari