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Design >> Analog Design >> Big Contributor of Phase Noise in Hysteresis Buffer
https://designers-guide.org/forum/YaBB.pl?num=1283950480

Message started by pancho_hideboo on Sep 8^th, 2010, 5:54am

Title: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 8^th, 2010, 5:54am

When I run a slave small signal noise analysis subjected to a master large signal driven PSS(Periodical Steady State) Analysis of a simple Hysteresis Inverter in attached figure, biggest contributor about phase noise at Vout is "MN3".

Do you think my result is reasonable ?

Anyway output phase noise of this Hysteresis Inverter is fairly worse compared to conventional inverter.

Do you think Hysteresis Inverter could produce larger phase noise ?

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by vp1953 on Sep 14^th, 2010, 4:54pm

Hi Pancho,

What are relative gm's for MN1, MN2 and MN3 say when the output is 1/2 VDD?

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by loose-electron on Sep 14^th, 2010, 6:20pm

You are applying a small signal analysis to a circuit which is significant in its large signal effects.

Plus small signal is not wisely applied to switching circuits - stay with PSS type techniques.

Also, hysterisys is a sense introduces a phase shift a a function of bias point and may not be the way to analyze the circuit.

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 15^th, 2010, 8:29am

vp1953 wrote on Sep 14^th, 2010, 4:54pm:

What are relative gm's for MN1, MN2 and MN3 say when the output is 1/2 VDD?

W/L of MN1 and MN2 are same. W/L of MN3 is smaller than MN1 and MN2.

"MM" is a size of MN1, MN2, MP1 and MP2 in attached figure.
"NN" is a size of MN3 and MP3 in attached figure.

loose-electron wrote on Sep 14^th, 2010, 6:20pm:

Plus small signal is not wisely applied to switching circuits - stay with PSS type techniques.

I don't think so at all.

Slave small signal noise analysis subjected to master large signal steady state analysis is enough helpful and valuable at least for relative comparisons, e.g. without hysteresis v.s. with hysteresis.

loose-electron wrote on Sep 14^th, 2010, 6:20pm:

Also, hysterisys is a sense introduces a phase shift a a function of bias point
and may not be the way to analyze the circuit.

I don't think so.

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 15^th, 2010, 9:54am

Attached figure shows time domain waveform for input and output.
I also show gradient of output.
As you can see, if width of hysteresis is wider, gradient of output is larger and sideband noise is also larger.

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by Mayank on Sep 17^th, 2010, 2:34am

Hi Pancho,

As Jerry said,

Quote:

Also, hystersys is a sense introduces a phase shift a a function of bias point and may not be the way to analyze the circuit.

In Hysteresis Inverter, you have two types of transition as is evident from the Hysteresis window. Do you think it is justified to treat both type of transitions driven by same Large Signal Solution ?
I dnt think so. Perform two separate analyses with their corresponding Large Signal Solutions, & then compile the noise analysis data in both the cases.

--Mayank.

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 17^th, 2010, 4:37am

Mayank wrote on Sep 17^th, 2010, 2:34am:

There is no reason why Large signal Steady State analysis can't capture transition effect, although I don't know what you mean by "two types of transition".

This is a small signal noise analysis averaged over one period which include both rise and fall edge's contributions.
See "deriv(out)" in http://www.designers-guide.org/Forum/Attachments/Hysteresis_2.png

Mayank wrote on Sep 17^th, 2010, 2:34am:

I dnt think so.
Perform two separate analyses with their corresponding Large Signal Solutions,

What do you mean by "their corresponding Large Signal Solutions" ?

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by vp1953 on Sep 18^th, 2010, 8:44am

Hi Pancho,

Your phase noise plot (titled USB_phase noise, lower right chart), how did you generate this? Can you please provide details.

Just a quick and dirty back of the envelope calculation shows close results - assuming gate thermal noise dominates, when NN=2 to 128, should close to 18dB of difference in the noise output. If I assume that the noise contribution is even between the PMOS and the NMOS devices, then varying NN would give about 15dB of difference - your plot shows 12db of difference in the phase noise as NN varies, so is fairly close.

As pointed by Mayank, the bias point is varying for the hysteretic circuit does vary and this alone should indeed produce some variation in the output phase noise, but i think this will cause no more than 1-2dB variation (I need to ponder a little more on this)

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 18^th, 2010, 12:37pm

vp1953 wrote on Sep 18^th, 2010, 8:44am:

Your phase noise plot (titled USB_phase noise, lower right chart), how did you generate this?

There is no such noise.
It is "USB Noise" not "USB Phase Noise".
See http://www.designers-guide.org/Forum/YaBB.pl?num=1274422891

Also see http://www.designers-guide.org/Forum/YaBB.pl?num=1280323054
Basically same as a link although this Hysteresis Buffer case is driven circuit not autonomous circuit.

vp1953 wrote on Sep 18^th, 2010, 8:44am:

Just a quick and dirty back of the envelope calculation shows close results - assuming gate thermal noise dominates,

Biggest contributor to output noise is a fricker noise of MN3 not thermal noise.

If size of MN3 is larger and then width of hysteresis is wider, sideband noise from MN3 is larger.
However total fricker noise of MN3 itself is smaller for larger MN3.

See "deriv(out)" in http://www.designers-guide.org/Forum/Attachments/Hysteresis_2.png
If a transition is sharper, output noise will be smaller generally.

But it is not true for my Hysteresis Buffer case.
I will survey about this more.

vp1953 wrote on Sep 18^th, 2010, 8:44am:

As pointed by Mayank, the bias point is varying for the hysteretic circuit does vary
and this alone should indeed produce some variation in the output phase noise,

Such thing is natural and common effect.
Consider "Bias dependent Noise" and then "Cyclostationary Noise".

Effects of periodical varying bias points are surely taken into Slave small signal noise analysis subjected to master large signal steady state analysis.

I think we can never escape fairly large degradation of phase noise if we implement Hysteresis characteristics having meaningful Hysteresis width.

I can see many cases where external TCXO signal is inputed via Hysteresis buffer for reference clock of PLL Synthesizer.
However could it cause very serious degradation of phase noise of PLL Synthesizer ?

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by vp1953 on Sep 19^th, 2010, 10:32am

Hi Pancho,

Quote:

Biggest contributor to output noise is a fricker noise of MN3 not thermal noise.

My bad, I misread that NN was the width of MN2 (it is the width of MN3). Now if flicker noise of MN3 is the biggest contributer, how do you explain your USB_noise going down with increasing width of MN3 : if it was flicker noise, then it should go down (gate thermal noise would cause it to go up in the manner shown in your plot)

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 19^th, 2010, 10:48am

pancho_hideboo wrote on Sep 15^th, 2010, 8:29am:

"MM" is a size of MN1, MN2, MP1 and MP2 in attached figure.
"NN" is a size of MN3 and MP3 in attached figure.

vp1953 wrote on Sep 19^th, 2010, 10:32am:

Now if flicker noise of MN3 is the biggest contributer, how do you explain your USB_noise going down with increasing width of MN3

Surely read following.

pancho_hideboo wrote on Sep 18^th, 2010, 12:37pm:

vp1953 wrote on Sep 18^th, 2010, 8:44am:

Just a quick and dirty back of the envelope calculation shows close results - assuming gate thermal noise dominates,

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by vp1953 on Sep 19^th, 2010, 12:23pm

Hi Pancho,

Higher noise from MN3 should produce higher USB noise. So if flicker noise goes down with increasing size of MN3(see below), then it cannot be that the USB noise increases. On the other hand gate thermal noise increases with increasing MN3 and this correlates well with your USB noise plots.

Also flicker noise decreases with device size if you are referring to input referred flicker noise voltage. For a common source stage, if you are referring to the output noise current, then both gate thermal noise (propotional to gm) and flicker noise current(proportional to gm^2/W) increase with W. In your circuit, obviously it is not a common source stage ;the exact relationship between input voltage and output current for MN3 needs some more examination because of the feedback.

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 19^th, 2010, 12:48pm

vp1953 wrote on Sep 19^th, 2010, 12:23pm:

On the other hand gate thermal noise increases with increasing MN3 and this correlates well with your USB noise plots.

Again, biggest contributor is fricker noise not channel noise.

I think large value of deriv(out) causes enhancement of cotribution to out from MN3's fricker noise.

vp1953 wrote on Sep 19^th, 2010, 12:23pm:

In your circuit, obviously it is not a common source stage

I can't understand what you want to mean.

MN1 and MN2 are formig common source stage.
MP1 and MP2 are also forming common source stage.

MN3 and MP3 are forming source follower stage.

Do you understand a working mechanism of this Hysteresis Inverter correctly ?

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by vp1953 on Sep 19^th, 2010, 2:23pm

HI Pancho

Quote:

Do you understand a working mechanism of this Hysteresis Inverter correctly ?

Yes i do :-)

Now you say flicker noise is the biggest contributer
You say flicker noise decreases with increase in size of MN3
Your plot shows increasing USB_noise with increase in size of MN3.
How this is possible - when the biggest contributer of noise is contributing less noise (with increasing device size), the USB noise is increasing? What is your explanation for this?

My reference to common source stage is to state the flicker noise decreases with device size only when considering the input referred noise voltage. If the flicker noise output current is considered, then flicker noise current can increase with device size for a common source stage (exact relation depends on topology).

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 19^th, 2010, 9:13pm

For fixed NN, increasing MM results in smaller output noise.
In this case, gain as inverter is also larger for larger MM.

On the other hand, for fixed MM, increasing NN results in larger output noise.
Also in this case, gain as inverter is larger for larger NN regardless of feedback.

vp1953 wrote on Sep 19^th, 2010, 2:23pm:

You say flicker noise decreases with increase in size of MN3
Your plot shows increasing USB_noise with increase in size of MN3.
How this is possible - when the biggest contributer of noise is contributing less noise (with increasing device size),
the USB noise is increasing? What is your explanation for this?

Do you understand a mechanism of contribution of fricker noise to sideband noise correctly ?

Contribution of fricker noise to sideband noise could be larger for sharp transition since conversion gain is larger.

Again do you understand a working mechanism of this Hysteresis Inverter correctly ?

BTW, have you been able to resolve the following ?
http://www.designers-guide.org/Forum/YaBB.pl?num=1283902372

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by vp1953 on Sep 20^th, 2010, 6:36pm

Hi Pancho

Quote:

Contribution of fricker noise to sideband noise could be larger for sharp transition since conversion gain is larger.

After thinking about this a little bit, I completely agree with you - this could be the reason. Basically stationary noise sources get convolved with response of the circuit to give your usb noise behaviour.

If flicker noise comes down with with increasing W, and USB noise increases with W, then the spectral components (fourier components, not PSD) at the output of your hysteretic invertor must increase by factor between varying between W^1/2 and W (a first order calculation). Is this the case for your circuit?

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by Alexandar on Sep 22^nd, 2010, 4:11am

I fear that the results of the upconversion of 1/f noise of the switches are not that accurate.
Did you checked the papers from Klumperink on this specific topic?

Title: Re: Big Contributor of Phase Noise in Hysteresis Buffer
Post by pancho_hideboo on Sep 22^nd, 2010, 6:34am

Lex wrote on Sep 22^nd, 2010, 4:11am:

I fear that the results of the upconversion of 1/f noise of the switches are not that accurate.
Did you checked the papers from Klumperink on this specific topic?

See http://www.designers-guide.org/Forum/YaBB.pl?num=1285083976

Fricker noise contribution is treated as upconversion from DC in any slave small noise analysis subjected to master large signal steady state analysis.

What are you fearing.

Indeed we can never evaluate sideband noise of very small offset frequency from carrier accurately even if we use any commercial simulator.
http://www.designers-guide.org/Forum/YaBB.pl?num=1050465395/20#20
http://www.designers-guide.org/Forum/YaBB.pl?num=1050465395/26#26
http://www.designers-guide.org/Forum/YaBB.pl?num=1263835149/6#6
http://www.designers-guide.org/Forum/YaBB.pl?num=1260521995/5#5